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Functional Verification Ethernet Verification IP

Advancements in JESD204C

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Advancements in JESD204C

As we know JESD204 standard describes a serial data interface between convertors and logic devices. In Revision A, the main expansion was to support both single and multiple lanes per convertor device. In Revision B,  mainly added features were programmable deterministic latency, usage of device clock as main clock source and data rate up to 12.5 Gbps. Now in the latest Revision C the data rate is increased up to 32 Gbps and three link layers have been introduced as 64B/66B, 64B/80B and 8B/10B where 8B/10B link layer is same as JESD204B link layer. JESD204C clearly defines layer wise relationship with the IEEE Ethernet model also. JESD204C defines mainly two categories of classes and each category contains three classes as shown in the table below.

  • Category B
  • Category C

Category

Class

Lane data rate (Gb/s)

B

B-3

0.3152-3.0125

B-6

0.3125-6.375

B-12

6.375-12.5

C

C-S

6.375-32

C-M

6.375-32

C-R

6.375-32

Category C is mainly defined for minimizing link power dissipation. The relative power efficiency of different classes of C category is as follows:

C Category Classes

Relative power

Power FFE

Receiver CTLE

Receiver DFE taps

C-S

Low

9.5dB

6dB

0

C-M

Medium

9.5dB

9dB

3

C-R

High

9.5dB

12dB

14

In JESD204C, the type of link layer which should be used depends on the required data rate as shown in the table below:

Data rate (DR) (Gbps)

8B/10B

64B/66B

64B/80B

DR<=6.375

Required

Not Recommended

Not Recommended

6.375

Required

Recommended

Optional

12.5

Optional

Required

Optional

In 8B/10B link layer, the data is organized into multiframes where in 64b/66b and 64b/80b link layers organize data into multiblocks of 32 blocks where each block contains 8 octets. In 8B/10B link layer, phase synchronization is done by Local Multiframe clock (LMFC) where as in 64B/66B and 64B/80B link layer uses the Local Extended Multiblock Clock (LEMC). In 8b/10b link layer, LMFC marks multiframe boundaries where as in 64B/66B and 64B/80B link layer LEMC is used to mark extended multiblock boundaries. In JESD204C, 8B10B link layer supports both subclass 1 and subclass 2 while 64B/66B and 64B/80B link layer supports only subclass 1. Deterministic latency can be achieved by both Local Multiframe clock (LMFC) or Local Extended Multiblock clock (LEMC) as per the link layer used.

The 8B/10B link layer does the alignment between multiple converter devices by the alignment of their LMFCs to an external signal SYSREF in subclass 1, and using the SYNC~ signal in subclass 2. In 64B/66B and 64B/80B link layer, the alignment between multiple converter devices is done by the alignment of their LEMC to an external signal SYSREF / MULTIREF in subclass 1. Each converter device can then adjust its LEMC phase to match with the common LEMC of the logic device. The 64B/66B and 64B/80B link layer only supports subclass 1 based LEMC alignment, it does not support subclass 2. In this case, the RBD adjustment resolution shall not be greater than 255 steps and if more than one multiframe or multiblock per lane fits in the buffer, the RBD adjustment resolution shall be at least 16 steps per multiframe or multiblock. The 64B/66B and 64B/80B link layer also defines a sync header stream, which transmits the information parallel to the user data. This information is encoded using the sync header portion of the 66B or 80B word block. One sync header per block is decoded to a single bit, and 32 of these bits across a multiblock makes a 32-bit sync word. The sync word can contain the following information:

  • Pilot signal (used to mark the borders of the multiblocks and extended multiblocks)
  • CRC-3 signal (used for error detection)
  • CRC-12 signal (used for error detection)
  • FEC signal (used for error detection and correction)
  • Command channel (used for transmitting commands and status information)

With the 8B/10B link layer, JESD204 uses the SYNC interface for synchronization and error reporting where as in 64B/66B or 64B/80B encoding sync headers within the encoded data are used for the synchronization process and the reporting of errors is left to the application layer. When all the converters in a device are inactive for a long period of time, it may be advantageous for the link to enter a shut-down mode. Operation in shutdown mode is similar to the continuous mode, but with power-down and power-up procedures applied between the periods of activity. These power-down and power-up procedures are not part of the current specification and their implementation is left to the application.

 
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