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Functional Verification Ethernet Verification IP

PCI Express Gen 4 for big data at high speed & Low power for emerging market applications

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PCI Express Gen 4 for big data at high speed & Low power for emerging market applications

PCI Express(PCIe) Gen 4 is the upper version of PCIe Gen 3, which superseded PCIe Gen 2 and Gen 1. The bandwidth provided by PCIe Gen 4 is double as compared to PCIe Gen 3. It is backward compatible with prior generations of PCI Express. PCIe Gen 4 is expected to satisfy, to a large extent, the requirements of high speed servers, gaming, graphics and data centers, where number of servers and solid-state devices are increasing as per market demand.

PCIe Gen 4 is the new evolution over the PCIe Gen 3. The PCIe Gen 4 provides the data rate of 16 G/Ts as compared to 8G/Ts provided by PCIe Gen 3. It’s architecture is fully compatible with all the earlier Generations of PCIe (Gen 3, Gen 2, Gen 1).

There are no changes in encoding scheme for Gen 4 and Gen 3 however Gen 4 provides more robust equalization. There are minor changes at protocol level and major changes at PHY interface for Gen 4. The throughput provided by Gen 4 is 16 GT/s per lane that is total bandwidth will be 32 GT/s (because of full duplex link support). PCIe Gen 4 provides L1 substates that lowers the power use in idle mode. This meets the requirements for high speed data transfer with minimum idle power. PCIe Gen 4 is a solution for emerging interfaces like Ethernet @400G, SSDs and flash memories which demand high speed. It’s performance bandwidth and throughput is also best suited for servers, data centers and graphics as per market demand for large data at high speed. 

Servers and storage applications:

High speed servers and data centers require, high speed storage which has led to the push for high speed data transfer and PCIe Gen4 has come up as a solution. Today’s servers have multi-core processors working at 2GHz with 256 bits of data. In a typical high-end server chip, there would be about 8 to 16 such processors, each of which could be dual (and some maybe even quad core). When one tries to network such high-speed processors, we need high speed interconnect, high speed memory and high speed data interface. Such a typical chip may require data throughput ranging from 128 gbps to 8 tbps. PCIe Gen4 which is the currently one of the fastest interface can support theoretical upto 1 tbps (considering full duplex and without considering the overheads/ efficiency). PCIe Gen 4 along with NVMe will help high speed storage applications.

Similarly gaming and graphics algorithm crunching chips also have multiple processors and require very high-speed data interface.

Some advantages of PCIe Gen 4 over previous generations:

  • Higher Speed of 16GT/s
  • Extended Capability for new lane margining feature
  • New Pipe Message Interface introduced for Lane Margining
  • Robust Equalization
  • New DLL feature state added to DLCMSM
  • NOP DLLP transmission for LCRC checking
  • Simplified replay timer
  • 10-bit tag introduced for increasing max number of outstanding TLPs
  • Scaled Flow Control for greater throughput
  • MSI-X with Steering Tag feature

PCIe is currently driving the CPU components like graphics cards, storage devices but gradually it’s becoming useful for big data at high speed. PCIe Gen 4 has emerged in the market at very crucial time for sever development and provides the support to electronics market. PCIe Gen 4 provides a solution for present demand in market for big data at very high speed with lower power consumption. The emerging areas covered by PCIe Gen 4 are networking applications, storage technologies, servers, data centers, graphics and gaming industries.

 

About Truechip’s PCIe Gen 4 Verification IP:

Truechip provides the Comprehensive Verification IP (C-VIP) of PCIe Gen 4. This PCIe C-VIP provides complete support for all Generations (Gen 1 to Gen 4). The C-VIP architecture optimizes link utilization, latency, reliability, power consumption. It is architected for power management, high link utilization, low latency and handles PCIe ordering rules, and implements flow control logic in both directions. It also supports PIPE 4.4.1 compliant PHYs and upto 64-bit pipe width as per user demand, and flexible lane ordering and support for lane reversal. This C-VIP is fully based on randomization, coverage, assertion and PCIe compliance testing. It allows maximum number of runtime configurable features and call backs. Truechip PCIe C-VIP also provides complete solution and easy integration into SoC designs.

 

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