Bridge IP
Truechip's Bridge IP provides chip designers and architects, an efficient way to connect Different Bus Protocol based IPs with reduced latency, power, and area
Key Benefits
- Available in native Verilog (RTL)
- Lintin, Synthesis, CDC, RDC are cleaned up.
- Verified with an expert team using comprehensive and Regression Test Suites.
- Consistency of interface, installation, operation, and documentation across all our IPs
- Easy GUI-based integration and configuration technique
- 24X5 customer support
- Unique and customizable licensing models
Features
- Support Any type of protocol conversion between Tilelink, Amba AXI,AHB,APB, Like AXI to Tilelink, AXI to AHB, AHB to APB, TL-UH to TL-UL etc.
- Interversion Transfer conversion like AHB5 to APB4
- Port data width can be different.
- Apart from data width, other protocol-supported signals can also have different widths.
- Support all type of transfers
- Breaking of transfer is possible
- Early response also possible for write transfer
- Support different phase-shifted frequencies for Master and Slaves
- Clock enable disable mechanism
- Support logical -physical address conversion
- Both little & high endianness is supported
- Arithmetic and logical transfer
- Enable buffering
- Interleaving support, Out of order transfer, Exclusives supports in AXI port
- Secure Transfer
- Support back-to-back transfers
- RegSlicing
Deliverables
- Bridge IP (required Master & slave bridge ports, Like Tilelink, AXI,AHB,APB)
- IP generator & config tool
- Verilog Test Environment with Verilog Testcases
- IP analysis reports
- Linting report
- Synthesis report
- IP-XACT RDL generated address map
- Simulation script
- IP Block Guide
- Quick Start Guide
