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HBM 3/2

Products >> Verification IP >> HBM 3/2

HBM 3 Verification IP

Truechip's HBM 3 Verification IP provides an effective & efficient way to verify the components interfacing with HBM interface of an ASIC/FPGA or SoC.

Truechip's HBM VIP is fully compliant with Standard HBM Version JESD235A specifications from JEDEC. This VIP is a light weight VIP with easy plug-and-play interface so that there is no hit on the design time and the simulation time.

Key Benefits

  • Available in native SystemVerilog (UVM/OVM/VMM) and Verilog.
  • Unique development methodology to ensure highest levels of quality.
  • Availability of Compliance & Regression Test Suites.
  • 24X5 customer support
  • Unique and customizable licensing models
  • Exhaustive set of assertions and cover points with connectivity example for all the components.
  • Consistency of interface, installation, operation and documentation across all our VIPs.
  • Provide complete solution and easy integration in IP and SoC environment.


  • Compliant to JEDEC HBM SDRAM Specification version JESD235A.
  • Supports Legacy and Pseudo Channel Mode.
  • Supports connection to any HBM Memory Controller IP communicating with a JESD235A compliant HBM Memory Model.
  • Available in all Stack memory size from 8 Gb to 32 Gb (8 Channels/Stack).
  • Available in Channel Density of 1 Gb(8 Banks/Channel), 2 Gb (8 Banks/Channel) or 4 Gb(16 Banks/Channel).
  • Data-Bus width : 1024 (128 DQ width/per Channel).
  • Supports Data Bus Inversion (DBIac) Feature.
  • Supports Parity Checking for Command/Address bus & Data bus.
  • Supports Data Mask for masking Write data per byte.
  • Supports configurable timing parameters and Channels-Die associations.
  • Supports capturing all the valid HBM Row & Column commands including Activate, Read, Write, Precharge in semi-independent way.
  • Supports Power-up Reset and initialization sequences.
  • Supports Power-Down, Self-Refresh operation.
  • Reports various timing error signals, which can be used to check for any timing errors.
  • Provides full control to the user to enable / disable various types of messages.
  • Integrates easily in any verification environment.
  • Supports full timing models or bus functional models.
  • Multiple instances of Monitor can be instantiated in a Verification Environment to support multiple Stacks.
  • Supports advanced System Verilog features like constrained random testing.
  • Supports Callback / User Configuration in Monitor, Controller and Memory Model BFMs.
  • Supports wide variety of Error Injection scenarios.
  • Supports Independent channel functioning.
  • Supports Testport feature.


  • HBM Controller BFM
  • HBM Monitor and Scoreboard
  • Test Environment & Test Suite:
    • Basic and Directed Protocol Tests
    • Random Tests
    • Error Scenario Tests
    • Assertions & Cover Point Tests
  • Integration Guide, User Manual and Release Notes.
Download the Product Brochure from here