Design Verification
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Functional Verification Ethernet Verification IP

JESD204B.01 Verification IP

Products >> Verification IPs >> JESD204B.01 Verification IP

JESD204B Verification IP

Truechip's JESD204B Verification IP provides an effective & efficient way to verify the components (data converters and/or logic devices) connecting with JESD204B ink. Truechip's JESD VIP is fully compliant with standard JESD204B.01 specification from JEDEC standard. This VIP is a light weight VIP with easy plug‐and‐play interface so that there is no hit on the design time.

Features

  • Support device subclass0, subclass1 and subclass2.
  • Supports serial data rate up to 12.5 Gbps.
  • Transmission of initial lane alignment sequence and alignmentcharacter.
  • Supports device class types‐ NMCDA‐SL, NMCDA‐ML, MCDA‐SL, MCDA‐ML.
  • Supports combining and non‐combining of SYNC~ signal.
  • Supports frame alignment monitoring and correction.
  • Supports lane alignment monitoring and correction.
  • Supports mechanism for achieving repeatable, programmable deterministic latency across link.
  • Supports up to 32 lanes.
  • Supports multiple samples per converter per frame cycle.
  • Scrambler can be enable or disable.
  • Supports error injection and detection in 8b/10 encoder/decoder.
  • Supports functional bus coverage and configuration coverage.
  • Supports comprehensive compliance test suit, Constraint random test cases and error injection test cases for verification.
  • Supports strong protocol monitoring.
  • Supports transaction logger for detail description of bus activity.
  • Supports bus assertions.

Deliverables

  • Transmitter Device Agent
  • Receiver Device Agent
  • Monitor and Scoreboard agent
  • Test environment and test suit
    • Basic and directed protocol tests
    • Random Tests
    • Error Scenario Tests
    • Assertions & Cover Point Tests
  • Integration Guide, User Manual, Presentations for VIP Integration
Download the Product Brochure from here