FutureWiz
loading...
Thank you for your query. We will reply to you at the earliest.

USB 3.1/3.0/2.0

Products >> Verification IP >> USB 3.1/3.0/2.0

USB 3.1 with xHCI Verification IP

Truechip's USB 3 .1 Verification IP provides an effective & efficient way to verify the components interfacing with USB 3.1 interface of an IP or SoC Truechip's USB 3.1 VIP is fully compliant with standard SuperSpeedPlus USB specifications from USB-IF. This VIP is a light weight VIP with easy plug-and-play interface so that there is no hit on the design cycle time.

Key Benefits

  • Available in native SystemVerilog (UVM/OVM/VMM) and Verilog
  • Unique development methodology to ensure highest levels of quality
  • Availability of Compliance & Regression Test Suites
  • 24X5 customer support
  • Unique and customizable licensing models
  • Exhaustive set of assertions and cover points with connectivity example for all the components
  • Consistency of interface, installation, operation and documentation across all our VIPs
  • Provide complete solution and easy integration in IP and SoC environment.

Features

  • Fully compliant with USB SuperSpeedPlus, xHCI 1.1 and PIPE v4.2 Specification with backward compatible to USB 3.0 and USB 2.0.
  • Supports upto 128 devices including hub and device on any tier level.
  • Supports 15 IN and 15 OUT and 1 control endpoint for each device.
  • Supports all transfer types; Control, Bulk,Bulk Stream, Interrupt with flow control and retry mechanism.
  • Support for pipelined isochronous and Smart Isochronous transfer.
  • Supports out of band active stream list exchange, HIMD and Stream Proposal rejection feature .
  • SuperSpeedPlus supports Simultaneous in Transactions with transaction re-ordering.
  • Supports bursting in all transfer modes (Upto max burst size).
  • SuperSpeedPlus supports Precision Time Measurement(PTM) and LDM protocol.
  • Supports Randomization for packet fields,protocol attributes,total transfer length (upto 1GB) and number of stream ID's.
  • Enhanced traffic and flow control management in link layer.
  • Two Block Types: Control Block and Data Block.
  • Type 1 And Type 2 traffic Classes.
  • Different Header packet framing for Deferred and Non- Deferred DPH.
  • Supports all compliance pattern for compliance LTSSM state.
  • Support TS1, TS2, TSEQ, SKP, SDS Ordered set generation.
  • Support for all power management states (U1, U2, U3).
  • Configurable PIPE Interface width 8,16 or 32 bits.
  • User controlled device attach/ detach function.
  • Less encoding overhead using 128/132 coding.
  • Comprehensive Compliance Test Suite for Protocol, Link, and Physical Layer verification.
  • Call backs support in all Layers to provide user control.
  • Supports all types of error injection and detection.
  • On the fly protocol checking using protocol check functions, static and dynamic assertion.
  • Built in coverage analysis.
  • Graphical analyser for all three Layers to show all transactions for easy debugging.

Deliverables

  • USB 3.1 Host/Device
  • USB 3.1 BFM/Agents for :
    • PHY Layer
    • Link Layer
    • Protocol Layer
  • USB 3.1 Layered Monitor and Scoreboard
  • Test Environment & Test Suite :
    • Basic and Directed Protocol Tests
    • Random Tests
    • Error Scenario Tests
    • Assertions & Cover Point Tests
    • Compliance Tests
    • Stress Test suit for protocol layer
  • Integration Guide, User Manual and Release Notes
  • GUI analyser to view simulation packet Flow
Download the Product Brochure from here