5+ years of work experience in ASIC IP cores design
Required: Bachelor's, Electrical Engineering Preferred: Master's, Electrical Engineering
Knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like UFS/EMMC/SPI is preferred.
Work closely with the SoC verification and validation teams for pre/post Silicon debug
Hands on experience in Low power design is required
Hands on experience in Multi Clock designs, Asynchronous interface is a must.
Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required.
Understanding of constraint development and timing closure is a plus.
Experience in Synthesis / Understanding of timing concepts is a plus.
Strong experience in micro architecting RTL design from high level design specification.
Excellent problem solving skills, strong communication and team work skills are mandatory.
Self-driven, needs to work with minimum supervision.
Experience in System Verilog, Verilog, C/C++, Perl and Python is a plus