NoC Verification

Truechip's NoC Verification IP provides an efficient & effective way to verify the NoC DUT .It is available in native Verilog, System Verilog and UVM. Compatible with Mentor Questa, Cadence NC/ Xcelium and Synopsys VCS simulator. It can be used in verification of Standalone NOC IP as well as in SoC environment .

Compliant with latest bus protocols like ARM® AHB3-Lite,5, ARM® AXI 3,4,4-Lite,5,5-Lite, ARM® APB 2,3,4,5 and SiFive TileLink Tl-UL, Tl-UH, TL-C with configurable protocols specified bus width. Users can configure each master and slave using the register configuration individually. Highly configurable Slave port address along with security, privilege and access permission.

Key Benefits

Available in native SystemVerilog (UVM/OVM/VMM) and Verilog
Unique development methodology to ensure highest levels of quality
24x5 customer support & response under 90 Min.
Unique and customizable licensing models
Exhaustive set of assertions and cover points with connectivity example for all the components
Consistency of interface, installation, operation and documentation across all our VIPs
Provide complete solution and easy integration in IP and SoC environment

Features

Complex network with acyclic agent graph (DAG). Layered and parallel NOC is also supported.
Any number of master and slave ports is supported. Each port can be configured individually.
ARM® AHB3-Lite,5, ARM® AXI 3,4,4-Lite,5,5-Lite, ARM® APB 2,3,4,5, SiFive TileLink Tl-UL, Tl-UH, TL-C.
Configurable memory map for different access types of memory regions.
Support for different protocols for master and slave port interfaces.
Each port data width can be different. Apart from the data, other protocols-supported signals can also have different widths.
Early write response possible.
Merging and breaking, both possible on transfers.
Support different phase-shifted frequencies for each Master and Slave.
Supported Qos throughout Noc
Support logical and physical conversion of address throughout NOC.
Both little and big endianness is support.
Configurable Default slave and Port Priority supported.
Capable of checking data integrity throughout NOC using NOC Scoreboard.
Configurable access methods, port security and privilege option Supported.
Different protocol with different phase shifted clock supported for each port.
Atomic transaction, NSAID signalling, Read data chunking, Interleaving support, Out of order transfer, Exclusive supports in AXI port.
Test Environment & Test Suite :
- Basic and Directed Protocol Tests
- Random Tests
- Error Scenario Tests
- Assertions & Cover Point Tests
- Compliance Tests
Provides detailed performance monitoring for all the transfers.
Supports advanced System Verilog features like constrained random testing.
Strong Protocol Monitor with real time exhaustive programmable checks.
Supports Dynamic as well as Static Error Injection scenarios.
On the fly protocol checking using protocol check functions, static and dynamic assertion
Graphical analyser to show transactions for easy debugging.

Deliverables

Monitor, Scoreboard & Matrix
Master and Slave Port VIP
AXI, AHB, APB, Tilelink Master, Slave, Monitor & Scoreboard
Integrated Testbench Example
TruEyE – Automated Testbench generation, Trace, Performance, Regression
Test Environment & Test Suite
Integration Guide, User Manual, FAQ and Release Notes

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NOC Performance

Truechip's NOC Performance provides robust performance analyzer for NOC IP/SoC. It can support fully compliant standard Bus interface ports like AXI, AHB, APB, TileLink etc.

Key Benefits

Unique development methodology to ensure the highest levels of quality
Availability of Compliance & Regression Test Suites
Exhaustive set of assertions and cover points with connectivity example for all the components.
Consistency of interface, installation, operation and documentation across all our VIPs
24X5 customer support
Unique and customizable licensing models

Features

Per interface latency
NoC latency
Per interface BW
Transaction Tracing
Master and Slave Interface comparisons(in terms of BW and Latency
Latency variation over the entire transactions
Count for transactions having minimum, maximum and average latencies
Consolidated summary timeline for different performance numbers in single window
Statistics Summary for different types of commands encountered on bus Bandwidth (GBps) and throughput Numbers
Actual Data transfer
Time window to select the duration for computing utilisation
Utilisation percentage in terms of total, Maximum, Minimum and Average utilisations

Deliverables

TruEye
NOC Monitor, Scoreboard
Master and Slave Port VIP (AXI/AHB/APB/Tilelink/……)
Test Suite:
- Basic and Directed Protocol Tests
- Random Tests
- Error Scenario Tests
- Assertions & Cover Point Tests
Integration Guide, User Manual, FAQ, and Release Notes

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Sub-System:

An IP subsystem is more than just a new and bigger type of IP block. A subsystem typically involves multiple related IP functions, each of which may be very large in its own right. These related IP functions combine to perform a new function, but must do so in a way that is applicable to a wide range of applications

Sub-System Verification:

Subsystem verification reduces the SoC verification cycle and it is more suitable to generate certain scenarios which are difficult to generate at top level.

Sub System Verification involves below scenarios:

Function Testing of the integrated IPs
Performance testing
Register accesses
GLS at Sub-System level for larger chips

TruEye Sub-System Verification IP Key Features:

Sub-System Memory Map: User will provide the memory map information of the Sub-system DUT to the GUI, along with tasks/ sequences to configure the peripherals.
Sub-System Verification can be done to verify only connectivity checks or full coverage verification.
Sub-System may contain one or more masters to initiate the transactions along with a NoC/ Crossbar or Fabric.
Sub-System may contain multiple peripherals for which VIPs will be automatically integrated and test cases will also be generated.
Sub-System Performance requirements are checked and summary is shared with the user.
Automated Regression and Regression Analysis are also provided.
Register Verification of Sub-system will also be performed by the Sub-System Verification IP.

Verification points for sub-system level :

Identifying all the data paths to the block.
Check the connectivity from the input port to the destination port.
Checking all the basic functionality expected from the system.
Measuring performance of the sub-system as it would behave on a chip level.
Observing the operation being performed on incoming and outgoing data from the sub-system.
Polling of interrupts generated from the sub-system

Advantages:

It checks whether the interconnectivity of different IPs that are integrated is intact.
Helps to verify the functionality of the complete system which would be used on a chip level.
Reduce the effort to verify the system at full chip.
The simulation run faster and the verification process is speeded up.
Any change in the RTL at IP level can tested at sub system easily.

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Automation Products

NoC Verification

NoC Performance

Sub-System Verification

Key Benefits

Features

Key Benefits

Features

TruEye Sub-System Verification IP Key Features:

Corporate Headquarters

Customer Support