NoC Verification

Truechip's NOC Verification IP provides an effective & efficient way to verify the components interfacing with any type of NOC IP or SoC. It has fully compliant standard Bus interface ports like AXI, AHB, APB, TileLink. This VIP is a light weight VIP with an easy plug-and-play interface so that there is no hit on the design cycle time. This solution comes with a GUI based TBG (testbench generation) method

Key Benefits

Available in native SystemVerilog UVM and Verilog
TruEye-TBG (Testbench generation)
Unique development methodology to ensure the highest
levels of quality
Availability of Compliance & Regression Test Suites
Exhaustive set of assertions and cover points with
Connectivity example for all the components.
Consistency of interface, installation, operation and documentation across all our VIPs
24X5 customer support
Unique and customizable licensing models

Features

Any number of master and slave port is possible
- End-To-End data integrity: Provides solution for data integrity
- through various scoreboard and checkers
- Different data width NOC ports - Each interface can have different data width
- Multi protocol NOC ports - Each interface can support different protocol
- Priority modes - Different priority modes when multi master try to access same slave at a time
- Visualization of Data flow: Data transfers can be visualized across NoC subsystems through different interface protocols
- Comprehensive test suite: Test generation for complete and robust verification of different bus interfaces
- Memory Mapped verification: Supports system mapped verification of Interfaces as well as different peripherals.
- Segmented slave memories also supported
- Transaction Verification: Provision to verify "Secure/ Non-Secure and Privileged/Non-Privileged " transactions
- All protocol required modes for selected protocols supported Like multiple outstanding of axi, busy transfer for ahb, Arithmetic transfers for Tilelink etc
- Generates full-fledged generic and customizable verification environment
- Multiple DUT and respective VIPs integration
- Generates different test scenarios and coverage models
- User can use existing sequence and also create new sequences
- User can select which sequence to be run on which environment
- User can select test features to be run on the environment
- Performance analysis of DUT

Deliverables

TruEye-TBG (Testbench generator)
- Master and Slave Port VIP (AXI/AHB/APB/Tilelink/……)
Test Suite:
- Basic and Directed Protocol Tests
- Random Tests
- Error Scenario Tests
- Assertions & Cover Point Tests
Integration Guide, User Manual, FAQ, and Release Notes

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NOC Performance

Truechip's NOC Performance provides robust performance analyzer for NOC IP/SoC. It can support fully compliant standard Bus interface ports like AXI, AHB, APB, TileLink etc.

Key Benefits

Unique development methodology to ensure the highest levels of quality
Availability of Compliance & Regression Test Suites
Exhaustive set of assertions and cover points with connectivity example for all the components.
Consistency of interface, installation, operation and documentation across all our VIPs
24X5 customer support
Unique and customizable licensing models

Features

Per interface latency
NoC latency
Per interface BW
Transaction Tracing
Master and Slave Interface comparisons(in terms of BW and Latency
Latency variation over the entire transactions
Count for transactions having minimum, maximum and average latencies
Consolidated summary timeline for different performance numbers in single window
Statistics Summary for different types of commands encountered on bus Bandwidth (GBps) and throughput Numbers
Actual Data transfer
Time window to select the duration for computing utilisation
Utilisation percentage in terms of total, Maximum, Minimum and Average utilisations

Deliverables

TruEye
NOC Monitor, Scoreboard
Master and Slave Port VIP (AXI/AHB/APB/Tilelink/……)
Test Suite:
- Basic and Directed Protocol Tests
- Random Tests
- Error Scenario Tests
- Assertions & Cover Point Tests
Integration Guide, User Manual, FAQ, and Release Notes

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Sub-System:

An IP subsystem is more than just a new and bigger type of IP block. A subsystem typically involves multiple related IP functions, each of which may be very large in its own right. These related IP functions combine to perform a new function, but must do so in a way that is applicable to a wide range of applications

Sub-System Verification:

Subsystem verification reduces the SoC verification cycle and it is more suitable to generate certain scenarios which are difficult to generate at top level.

Sub System Verification involves below scenarios:

Function Testing of the integrated IPs
Performance testing
Register accesses
GLS at Sub-System level for larger chips

TruEye Sub-System Verification IP Key Features:

Sub-System Memory Map: User will provide the memory map information of the Sub-system DUT to the GUI, along with tasks/ sequences to configure the peripherals.
Sub-System Verification can be done to verify only connectivity checks or full coverage verification.
Sub-System may contain one or more masters to initiate the transactions along with a NoC/ Crossbar or Fabric.
Sub-System may contain multiple peripherals for which VIPs will be automatically integrated and test cases will also be generated.
Sub-System Performance requirements are checked and summary is shared with the user.
Automated Regression and Regression Analysis are also provided.
Register Verification of Sub-system will also be performed by the Sub-System Verification IP.

Verification points for sub-system level :

Identifying all the data paths to the block.
Check the connectivity from the input port to the destination port.
Checking all the basic functionality expected from the system.
Measuring performance of the sub-system as it would behave on a chip level.
Observing the operation being performed on incoming and outgoing data from the sub-system.
Polling of interrupts generated from the sub-system

Advantages:

It checks whether the interconnectivity of different IPs that are integrated is intact.
Helps to verify the functionality of the complete system which would be used on a chip level.
Reduce the effort to verify the system at full chip.
The simulation run faster and the verification process is speeded up.
Any change in the RTL at IP level can tested at sub system easily.

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Automation Products

NoC Verification

NoC Performance

Sub-System Verification

Key Benefits

Features

Key Benefits

Features

TruEye Sub-System Verification IP Key Features:

Corporate Headquarters

Customer Support