Sub-System:
An IP subsystem is more than just a new and bigger type of IP block. A subsystem typically involves multiple related IP functions, each of which may be very large in its own right. These related IP functions combine to perform a new function, but must do so in a way that is applicable to a wide range of applications
Sub-System Verification:
Subsystem verification reduces the SoC verification cycle and it is more suitable to generate certain scenarios which are difficult to generate at top level.
Sub System Verification involves below scenarios:
- Function Testing of the integrated IPs
- Performance testing
- Register accesses
- GLS at Sub-System level for larger chips
TruEye Sub-System Verification IP Key Features:
- Sub-System Memory Map: User will provide the memory map information of the Sub-system DUT to the GUI, along with tasks/ sequences to configure the peripherals.
- Sub-System Verification can be done to verify only connectivity checks or full coverage verification.
- Sub-System may contain one or more masters to initiate the transactions along with a NoC/ Crossbar or Fabric.
- Sub-System may contain multiple peripherals for which VIPs will be automatically integrated and test cases will also be generated.
- Sub-System Performance requirements are checked and summary is shared with the user.
- Automated Regression and Regression Analysis are also provided.
- Register Verification of Sub-system will also be performed by the Sub-System Verification IP.
Verification points for sub-system level :
- Identifying all the data paths to the block.
- Check the connectivity from the input port to the destination port.
- Checking all the basic functionality expected from the system.
- Measuring performance of the sub-system as it would behave on a chip level.
- Observing the operation being performed on incoming and outgoing data from the sub-system.
- Polling of interrupts generated from the sub-system
Advantages:
- It checks whether the interconnectivity of different IPs that are integrated is intact.
- Helps to verify the functionality of the complete system which would be used on a chip level.
- Reduce the effort to verify the system at full chip.
- The simulation run faster and the verification process is speeded up.
- Any change in the RTL at IP level can tested at sub system easily.