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Automation Products

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NoC Verification

NoC Performance

Sub-System Verification

NoC Verification

Truechip's NOC Verification IP provides an effective & efficient way to verify the components interfacing with any type of NOC IP or SoC. It has fully compliant standard Bus interface ports like AXI, AHB, APB, TileLink. This VIP is a light weight VIP with an easy plug-and-play interface so that there is no hit on the design cycle time. This solution comes with a GUI based TBG (testbench generation) method

Key Benefits

  • Available in native SystemVerilog UVM and Verilog
  • TruEye-TBG (Testbench generation)
  • Unique development methodology to ensure the highest
  • levels of quality
  • Availability of Compliance & Regression Test Suites
  • Exhaustive set of assertions and cover points with
  • Connectivity example for all the components.
  • Consistency of interface, installation, operation and documentation across all our VIPs
  • 24X5 customer support
  • Unique and customizable licensing models


  • Any number of master and slave port is possible
    • End-To-End data integrity: Provides solution for data integrity
    • through various scoreboard and checkers
    • Different data width NOC ports - Each interface can have different data width
    • Multi protocol NOC ports - Each interface can support different protocol
    • Priority modes - Different priority modes when multi master try to access same slave at a time
    • Visualization of Data flow: Data transfers can be visualized across NoC subsystems through different interface protocols
    • Comprehensive test suite: Test generation for complete and robust verification of different bus interfaces
    • Memory Mapped verification: Supports system mapped verification of Interfaces as well as different peripherals.
    • Segmented slave memories also supported
    • Transaction Verification: Provision to verify "Secure/ Non-Secure and Privileged/Non-Privileged " transactions
    • All protocol required modes for selected protocols supported Like multiple outstanding of axi, busy transfer for ahb, Arithmetic transfers for Tilelink etc
    • Generates full-fledged generic and customizable verification environment
    • Multiple DUT and respective VIPs integration
    • Generates different test scenarios and coverage models
    • User can use existing sequence and also create new sequences
    • User can select which sequence to be run on which environment
    • User can select test features to be run on the environment
    • Performance analysis of DUT


  • TruEye-TBG (Testbench generator)
    • Master and Slave Port VIP (AXI/AHB/APB/Tilelink/……)
  • Test Suite:
    • Basic and Directed Protocol Tests
    • Random Tests
    • Error Scenario Tests
    • Assertions & Cover Point Tests
  • Integration Guide, User Manual, FAQ, and Release Notes