Verification IP

Truechip's Verification IP (VIP) provides an effective and efficient way to verify the components interfacing with industry-standard protocols in an ASIC/FPGA or SOC.
Our Verification IPs are fully compliant with standard specifications and come with an easy plug-and-play interface so that there is no hit on the design and development cycle time. Key Benefits of Truechip Verification IP's are - 

• All VIPs include Coverage, Assertions, BFMs, Monitors, Scoreboard, and Test Cases.
• All VIPs supports a wide variety of error injection scenarios to help stress test the DUT.
• Native SystemVerilog architecture is optimized for minimal compute resource usage.
• All VIPs is highly configurable, giving the user complete control.
• Truechip VIPs have Spec tagging of features -
  • Spec tagging of features for test plan
  • Spec tagging of features for Monitor check plan
  • Spec tagging of features for Assertion plan
  • Spec tagging of features for the Coverage plan
• Assertions -
  • In addition to what competition delivers, we also provide Assertions with the VIP. 
  • These assertions can be used in formal verification as well as dynamic verification
  • These assertions can also be used for emulation
• Platform Independent Verifications IP
  • Work with all industry-leading dynamic and formal verification simulators
  • Emulation and acceleration support available
• All Truechip Verification IP comes with User-friendly Documentation includes -
  • User Manual - list all the configurations of the Verification IP
  • Integration Guide - for the different scenarios of VIP/DUT integration
  • Integration PPTs for quick integration references
  • FAQ docs for frequently asked questions
• TruEYE GUI and Debugging Support - 
  • Easy debugging support with TruEYE GUI and debug log files