Verification IP | Truechip

Verification IP Portfolio
USB USB 4 v2 USB 4.0 UAS USB 4/3/2 HUB Retimer 4.0/3.2 128b / 132b USB 3.2/3.1/3.0 USB 2.0 USB2 OTG eUSB USB PD v3.1 Type C v 1.3 xHCI	BUS/Interface UCIe 2.0 UCIe with Retimer BOW CPRI/eCPRI JESD204D/C/B SMBUS v3.2 xSPI SPI/QSPI/OSPI RTC PMBUS v1.4 I2C/I2S UART/USART JTAG	MIPI A-PHY / PAL MASS SPMI CSI-2 v4.0.1 I3C v1.1.1 I3C basic v1.1.1 DSI-2 v2.1 DSI v1.3.2 C-PHY v2.1 D-PHY v3.5 M-PHY v5.0 Unipro v2.0	Automotive Automotive Eth TSN TSN Que & Fwd PTP/ gPTP MAC Sec Preemption / PFC ASA FlexRay CAN CXPI SENT / LIN	SoC/Avionics PWM WDT PIT GPIO 8b / 10b 64b / 66b SpaceWire ARINC429 ARINC708A SMPTE SDI MIL-STD-1553	Networking TCP/TCPSW 800G 400G/200G 100G/40G QBV 50G/25G 10G/5G/2.5G 1G/100M/10M IPSec Interlaken v 1.2	Storage NVME 2.0/1.4 UFS 4 / 3.1 UHS 3/2/1 ONFI 5.0 SD Express/SD8 SDUC/SDXC SDIO/SDHC SATA 3.3 eMMC v5.1a	AMBA CHI 5 AXI 5 / 5 Lite ACE 4 / 4 Lite AXI Stream 5/4 AHB 5/3 Lite AXI4/4 Lite/3 CXS a/b APB 5/4/3 ATB 5/4/3	PCIe CXL 3/2 Gen 6 CXL Switch PCIe Switch Gen 5/4 Gen 3/2 PIPE 6/5 SRIOV ATS	Memory DDR5/4/3 LPDDR5 / 5x LPDDR 4x/4/3 HBM 3/2 RDIMM/LRDIMM GDDR6 HMC	Display DP 2.1 DP 2.0/1.4 LVDS LTTPR/MST eDP 1.5/1.4b HDMI 2.1/2.0/1.4 HDCP 2.4/2.3/1.4	RISC V TileLink RI5CY FPU JTAG DTM PLIC

Verification IP Portfolio

USB

USB 4 v2

USB 4.0

UAS

USB 4/3/2 HUB

Retimer 4.0/3.2

128b / 132b

USB 3.2/3.1/3.0

USB 2.0

USB2 OTG

eUSB

USB PD v3.1

Type C v 1.3

xHCI

BUS/Interface

UCIe 2.0

UCIe with Retimer

BOW

CPRI/eCPRI

JESD204D/C/B

SMBUS v3.2

xSPI

SPI/QSPI/OSPI

RTC

PMBUS v1.4

I2C/I2S

UART/USART

JTAG

MIPI

A-PHY / PAL

MASS

SPMI

CSI-2 v4.0.1

I3C v1.1.1

I3C basic v1.1.1

DSI-2 v2.1

DSI v1.3.2

C-PHY v2.1

D-PHY v3.5

M-PHY v5.0

Unipro v2.0

Automotive

Automotive Eth

TSN

TSN Que & Fwd

PTP/ gPTP

MAC Sec

Preemption / PFC

ASA

FlexRay

CAN

CXPI

SENT / LIN

SoC/Avionics

PWM

WDT

PIT

GPIO

8b / 10b

64b / 66b

SpaceWire

ARINC429

ARINC708A

SMPTE SDI

MIL-STD-1553

Networking

TCP/TCPSW

800G

400G/200G

100G/40G

QBV

50G/25G

10G/5G/2.5G

1G/100M/10M

IPSec

Interlaken v 1.2

Storage

NVME 2.0/1.4

UFS 4 / 3.1

UHS 3/2/1

ONFI 5.0

SD Express/SD8

SDUC/SDXC

SDIO/SDHC

SATA 3.3

eMMC v5.1a

AMBA

CHI 5

AXI 5 / 5 Lite

ACE 4 / 4 Lite

AXI Stream 5/4

AHB 5/3 Lite

AXI4/4 Lite/3

CXS a/b

APB 5/4/3

ATB 5/4/3

PCIe

CXL 3/2

Gen 6

CXL Switch

PCIe Switch

Gen 5/4

Gen 3/2

PIPE 6/5

SRIOV

ATS

Memory

DDR5/4/3

LPDDR5 / 5x

LPDDR 4x/4/3

HBM 3/2

RDIMM/LRDIMM

GDDR6

HMC

Display

DP 2.1

DP 2.0/1.4

LVDS

LTTPR/MST

eDP 1.5/1.4b

HDMI 2.1/2.0/1.4

HDCP 2.4/2.3/1.4

RISC V

TileLink

RI5CY

FPU

JTAG DTM

PLIC

Truechip's Verification IP (VIP) provides an effective and efficient way to verify the components interfacing with industry-standard protocols in an ASIC/FPGA or SOC.

Truechip Verification IP are fully compliant with standard specifications and come with an easy plug-and-play interface so that there is no hit on the design and development cycle time.

Key Benefits of Truechip Verification IP is -

All Verification IP include Coverage, Assertions, BFMs, Monitors, Scoreboard, and Test Cases.
All VIPs support a wide variety of error injection scenarios to help stress test the DUT.
Native SystemVerilog architecture is optimized for minimal compute resource usage.
All VIPs are highly configurable, giving the user complete control.
Truechip VIPs have Spec tagging of features -
- Spec tagging of features for test plan
- Spec tagging of features for Monitor check plan
- Spec tagging of features for the Assertion plan
- Spec tagging of features for the Coverage plan
Assertions -
- In addition to what competition delivers, we also provide Assertions with the VIP.
- These assertions can be used in formal verification as well as dynamic verification
- These assertions can also be used for emulation

Platform Independent Verifications IP
- Work with all industry-leading dynamic and formal verification simulators
- Emulation and acceleration support are available

All Truechip Verification IP comes with User-friendly Documentation including -
- User Manual - list all the configurations of the Verification IP
- Integration Guide - for the different scenarios of VIP/DUT integration
- Integration PPTs for quick integration references
- FAQ docs for frequently asked questions

TruEYE GUI and Debugging Support -
- Easy debugging support with TruEYE GUI and debug log files

Verification IPs

Verification IP Portfolio

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