SpaceWire Verification IP

Truechip's SpaceWire Verification IP provides an effective & efficient way to verify the components interfacing with SpaceWire interface of an ASIC/FPGA or SoC.
 Truechip's SpaceWire VIP is fully compliant with ECSS-E-ST-50-12 C rev 1 specification of SpaceWire. This VIP is a lightweight with an easy plug-and-play interface so that there is no hit on the design time and the simulation time.

Key Benefits

• Available in native System Verilog (UVM/OVM/ VMM) and Verilog
• Unique development methodology to ensure the highest levels of quality
•  Availability of Compliance & Regression Test Suites
•  24X5 customer support
•  Unique and customizable licensing models
•  Exhaustive set of coverage points with connectivity example for all the components
•  Consistency of interface, installation, operation, and documentation across all our VIPs
•  Provide complete solution and easy integration in IP and SoC environment

Features

• Full duplex communication with a different speed enabled (Supported speeds 2Mb/s- 400Mb/s and higher as per user requirement) in each direction of communication
• Encoding layer performs synchronization(first null), parity calculation/check, serialization/deserialization with  Data-Strobe encoding/decoding
• Encoding layer can indicate errors to DLL 
• DLL and Encoding layer capable of handling all data and control characters with inbuilt flow control
• DLL supports link initialization and link recovery as per state machines specified
• DLL adheres  to priority ordering in data flow when sending data and control characters 
• Network layer capable of handling SpaceWire packets, time codes and interrupt codes
• Service Interface between each layer for easy debug and integration
• Routing of SpaceWire packets from corresponding input to output ports
• Path and logical addressing when using routing switches (i.e. selection though configuration)
• Time Code register updation and time code distribution capable
• Handling of all distributed interrupts as configured through interrupt relay register
• Configurable routing table
• Capable of handling routing switch errors
• Optional deletion of address when using logical addressing
• Controlled arbitration from output port access
• Configurable multicast scheme with routing switch
• Support present for RMAP with SpaceWire as per ECSS‐E‐ST‐50‐52C
• TC configuration interface for single point configurability from test/sequence
• All management parameters including link speed, link start, AutoStart, PortReset supported thought TC configuration interface
• All specification defined timer and counter values configurable from test and sequence level
• Fine-tuned user control for environment build and configuration for each test distinctly
• Callbacks for error injection at each level of data flow for dynamic and targeted error injection
• Auto Masking capability in Monitors for Errors deliberately Injected
• Configurable message/error handling/reporting with on the fly options from test/sequence
• TC Scoreboard proving end to end SpaceWire packet data integrity checks
• Comprehensive test suite 
• Functional coverage at each component level
• Graphical analyzer to show transactions for easy debugging

Deliverables

• SpaceWire BFM’s having

  • Network Layer

  • Link-layer

  • Encoding and Physical Layer

  • Routing Switch 

• Monitor proving protocol-specific checks at each level of functionality
• Scoreboard providing end to end packet integrity check
• Integration guide, user manual, quick start guide, and release notes
• Test suite
  • Basic Tests
  • Random Test Suite
  • Error Injection Test
  • Cover Point Specific Tests
  • User-Defined Test
• GUI (TrueEye)