Design Verification
loading...
Thank you for your query. We will reply to you at the earliest.
Functional Verification Ethernet Verification IP

Gen 6

Products >> Verification IP >> Gen 6

PCIe Gen 6 Verification IP

Truechip's PCIe Gen 6 Verification IP provides an effective & efficient way to verify the components interfacing with PCIe Gen 6 interface of an IP or SoC Truechip's PCIe Gen 6 VIP is fully compliant with the latest PCI Express Gen 6 specifications. This VIP is lightweight with an easy plug-and-play interface so that there is no hit on the design cycle time.

Key Benefits

  • Available in native SystemVerilog (UVM/OVM/VMM) and Verilog
  • Unique development methodology to ensure the highest levels of quality
  • 24X5 customer support
  • Unique and customizable licensing models
  • Exhaustive set of assertions and cover points with connectivity example for all the components
  • Consistency of interface, installation, operation, and documentation across all our VIPs
  • Provide complete solution and easy integration in IP and SoC environment.

Features

  • Compliant with PCI Express Specifications 6.0 v0.7(64GT/s), 5.0 v1.0(32GT/s), 4.0 v1.0 (16GT/s), 3.0 (8GT/s), 2.0 (5GT/s) and 1.1 (2.5GT/s).
  • Support for 64.0 GT/s Data Rate per lane with backwards compatible.
  • Lower pin count in pipe interface when supporting 64.0 GT/s.
  • Support for Serdes PIPE architecture at 64 GT/s.
  • Support for PAM4 Signalling and Gray Coding.
  • Support for both Flit Mode & Non Flit Mode.
  • Support for TS0 ordered set (Equalization at 64bit).
  • Support for Precoding at 32GT/s and 64GT/s.
  • Compliant with PIPE Specification 6.0
  • Support for New Power Management state L0p.
  • Verification IP configurable as PCI express Root Complex and Device Endpoint.
  • Configurable LinkWidth: x1, x2, x4, x8, x12, x16, x32.
  • Configurable original pipe width : 8,16,32,64 and for Serdes Architecture: 10, 20, 40, 80
  • Supports Low Power management LTSSM states - L0s, L1, L2, L1 sub-states, PCI- PM, ASPM.
  • Supports 14-bit Tag as requester as well as a completer.
  • Supports Non-Posted Deferrable Memory Writes.
  • Support for NOP TLPs.
  • Advanced Error Reporting (AER) with optional Malformed TLP checks, ECRC, and TLP Poisoning support.
  • Support for Shared Flow Control Mechanism.
  • Compliance testing in TL, DLL & PL including power management test-suites.
  • Support for Flit Logging Extended Capability. Ø Support for optional extended capabilities such as:
    • Shadow Function Extended Capability
    • Data Object Exchange Extended Capability
    • VF Resizable Bar Extended Capability
    • Flit Error Injection Extended Capability
  • On-the-fly protocol checking using protocol check functions, static and dynamic assertion.
  • Built-in Coverage analysis.
  • Provides a comprehensive user API (callbacks).
  • Graphical analyzer for all three Layers to show PCIe transactions for easy debugging.
  • Supports simplified replay timer and SR-IOV
  • Support for ATS with the latest ATS Specification revision 1.1.
  • Supports LTR & FLR (Function Level Reset)

Deliverables

  • PCIe Gen 6 Root-Complex/Device-Endpoint
  • PCIe Gen 6 BFM/Agents for:
    • PHY Layer
    • Data Link Layer
    • Transaction Layer
    • Register Space
  • PCIe Gen 6 Layered Monitor and Scoreboard
  • Test Environment & Test Suite:
    • Basic and Directed Protocol Tests
    • Random TestsError Scenario Tests
    • Assertions & Cover Point Tests
    • Compliance Tests
  • Integration Guide, User Manual, and Release Notes
Download the Product Brochure from here