LPDDR4X Verification IP

Truechip's LPDDR4X Verification IP provides an effective & efficient way to verify the components interfacing with the LPDDR4X interface of an ASIC/FPGA or SoC. Truechip's LPDDR4X VIP is fully compliant with Standard LPDDR4X Version JESD209-4-1 specifications from JEDEC. This VIP is a lightweight VIP with an easy plug-and-play interface so that there is no hit on the design time and the simulation. time.

Key Benefits

• Available in native System Verilog (UVM/OVM/VMM) and Verilog
• Unique development methodology to ensure the highest levels of quality
• Availability of various Regression Test Suites
• 24X5 customer support
• Unique and customizable licensing models
• Exhaustive set of assertions and cover points with connectivity examples for all the components
• Consistency of interface, installation, operation, and documentation across all our VIPs
• Provide complete solutions and easy integration in IP and SoC environment

Features

• Compliant with JEDEC LPDDR4X Specification version JESD209-4-1.
• Supports LPDDR4X memory devices from all leading vendors.
• Supports multiple densities: 4Gb to 32Gb.
• Supports all lpddr4x ODT CA/CS/CKT control via MRS register
• Supports all the timing changes in lpddr4x as per spec.
• Supports all the default values of MR register as per lpddr4x spec.
• Supports all the voltage ranges in mr register as per lpddr4x spec.
• Supports capturing of all the valid LPDDR4X commands as per the specs
• Supports dual channels which can function independently.
• Supports Data Bus Inversion and Data Masking(DM).
• Support for all speed grades/speed bins.
• Support for Multiple Ranks architecture.
• Supports Programmable READ/WRITE Latency timings
• Supports programming of All-Mode Registers.
• Support CA training and DQ calibration.
• Support write data mask and data strobe features.
• Support for Power Down features.
• Support for all timing delay ranges in one model: min and max.
• Reports various timing errors, which can be used to check any timing violations.
• Provides full control to the user to enable/disable various types of messages.
• Supports advanced SystemVerilog features like constrained random testing.
• Strong Protocol Monitor with real-time exhaustive programmable checks.
• Supports Dynamic as well as Static Error Injection scenarios.
• On-the-fly protocol checking using protocol check functions, static and dynamic assertion.
• Built-in Coverage analysis.
• Provides a comprehensive user API (callbacks) in Monitor, Controller, and Memory Model BFMs.
• Graphical analyzer to show transactions for easy debugging.

Deliverables

• LPDDR4X-SDRAM Model.
• LPDDR4X Monitor and Scoreboard.
• LPDDR4X Memory Controller BFM/Agent
• LPDDR4X PHY BFM model.
• LPDDR4X Phy Monitor and Scoreboard.
• Test-Bench Configurations.
• Test Suite (Available in Source code) :
  • Basic Protocol Tests.
  • Directed & Random Tests.
  • Assertion and Cover Point Tests.
• Integration Guide, User Manual, and Release Notes.
• GUI analyzer to view simulation packet Flow.​