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DSI-2 v2.1

Products >> Verification IP >> DSI-2 v2.1

MIPI DSI with C-PHY Verification IP

Truechip's MIPI DSI with C-PHY Verification IP provides an effective and efficient way to verify the components interfacing with MIPI DSI with CPHY interface of an IP and SOC. Truechip's MIPI DSI with C-PHY VIP is fully compliant to MIPI DSI Specification version 1.3.2 along with MIPI C-PHY Specification version 2.1. The VIP is light weight with easy plug-and- play interface so that there is no hit on the design cycle time

Key Benefits

  • Available in native System Verilog (UVM/OVM/VMM) and Verilog
  • Unique development methodology to ensure the highest levels of quality
  • Availability of Compliance & Regression Test Suites
  • 24X5 customer support
  • Unique and customizable licensing models
  • Exhaustive set of assertions and coverage points with connectivity examples for all the components
  • Consistency of interface, installation, operation, and documentation across all our VIPs
  • Provide complete solutions and easy integration in IP and SoC environment


  • Compliant to MIPI DSI Specification version 1.3.2 and MIPI C-PHY Specification version 2.1 with PPI interface.
  • Support all Calibration Format & operations
  • C-PHY supports MFAA and SFAA for DSI TX and RX respectively for Data Lane Module in command mode.
  • C-PHY supports MFAN and SFAN for DSI TX and RX respectively for data Lane Module in video mode.
  • Configurable number of Data Lanes and Sub Links.
  • Supports Data Lane distribution and merging in case of multitiLane configuration.
  • Supports High-Speed , Low Power Escape, Control modes.
  • Supports 16:7 Mapper and 7:16 Demapper.
  • Supports symbol encoding and decoding.
  • Supports dynamically configurable modes.
  • Supports all Short and Long packet formats.
  • Supports ECC and CRC generation as well as correction/detection.
  • Supports End of Transmission packet along with EOT Sequence.
  • Strong Protocol Monitor with real time exhaustive programmable checks available for each LLP, LM and PHY layer.
  • Supports Dynamic as well as Static Error Injection scenarios at both Protocol and PHY layer.
  • On the fly protocol checking using protocol check functions, static and dynamic assertion.
  • Built in Coverage analysis.
  • Provides a comprehensive user API (callbacks) in Transmitter and Receive.
  • Graphical analyser for all Layers to show transactions for easy debugging.


  • MIPI DSI Monitor and Score board
  • Testbench Configurations
  • Test Suite (Available in Source Code)
    • Basic and Directed Protocol Tests
    • Random Tests
    • Error Scenario Tests
    • Assertions & Coverage Tests
    • Integration Guide, User Manual and Release Notes
Download the Product Brochure from here