Design Verification
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Functional Verification Ethernet Verification IP


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Ethernet TSN Verification IP

Truechip's Ethernet TSN Verification IP provides an effective & efficient way to verify the components interfacing with an IP or SoC.

Truechip's Ethernet TSN VIP is fully compliant with IEEE standard 802.3-2015 specification and TSN features as compliant to the standards mentioned by the IEEE 802.1 working group. This VIP is light weight with easy plug-and- play interface so that there is no hit on the design cycle time.

Key Benefits

  • Available in native System Verilog (UVM/OVM/ VMM) and Verilog
  • Unique development methodology to ensure highest levels of quality
  • Availability of Compliance & Regression Test Suites
  • 24X5 customer support
  • Unique and customizable licensing models
  • Exhaustive set of assertions and coverage points with connectivity example for all the components
  • Consistency of interface, installation, operation and documentation across all our VIPs
  • Provide complete solution and easy integration in IP and SoC environment​


  • Provides TSN timing synchronization
    • Capable of timing synchronization using gPTP(as per IEEE 802.1AS)
    • Supports PTP peer delay protocol to measure propagation delay on point-to-point links
    • BMCA determination is supported
    • Frame Preemption support with system level interface to manage express traffic is present
  • Capable of transmission and reception of interspersed traffic
  • Capable of traffic flow control using a time aware scheduler and credit based scheduler
  • Support present for stream reservation protocol for path control and reservation, frame replication /elimination and fault tolerance
  • Support present for Link Aggregation as per IEEE 802.1AX-2014
  • Support for cyclic queuing and forwarding using deterministic delay calculation algorithm
  •  Provides Ethernet fully compliant as per IEEE 802.3-2015
    • Supports standard Media Independent Interface(1/10/25/40/50 /100/200/400G)
    • Supports Auto negotiation for link speed negotiation(1/10/25/40 /50/100/200G)
    • MAC-Sec support present
    • Supports Pause Frame Based Flow Control
    • Capable of handling LLDP packet exchange
    • Provides EEE capability
    • Supports all possible widths for PCS/FEC to serdes interface
    • Supports clock data recovery(CDR)
    • Supports for MMD registers, MDIO interface supported
  • Callback support in layers to provide user control
  • Rich set of configuration and parameters
  • Provides static as well as dynamic error injection capability
  • On the fly protocol checking static and dynamic assertion
  • Built in coverage analysis
  • Graphical analyser to show transactions for easy debugging 


Download the Product Brochure from here