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Products >> Verification IP >> GDDR6

GDDR6 Verification IP

Truechip's GDDR6 Verification IP provides an effective & efficient way to verify the components interface with the GDDR6 interface of an ASIC/FPGA or SoC. Truechip's GDDR6 VIP is fully compliant with Standard GDDR6 Version JESD250B specification from JEDEC. This VIP is a lightweight with an easy plug-and-play interface so that there is no hit on the design time and the simulation time.

Key Benefits

  • Available in native SystemVerilog (UVM/OVM/VMM) and Verilog
  • Unique development methodology to ensure the highest levels of quality
  • Availability of various Regression Test Suites
  • 24X5 customer support
  • Unique and customizable licensing models
  • Exhaustive set of assertions and cover points with connectivity example for all the components
  • Consistency of interface, installation, operation, and documentation across all our VIPs
  • Provide complete solution and easy integration in IP and SoC environment


  • Compliant to JEDEC GDDR6 SDRAM Specification version JESD250B.
  • Supports connection to any GDDR6 Memory Controller IP communicating with a JESD250B compliant GDDR6 Memory Model.
  • Supports configurable SDRAM addressing of different sizes (x8 and x16).
  • Available in all memory sizes from 4 Gb to 16 Gb per channel.
  • Supports multi-channel.
  • Supports Double and Quad data rates for WCK
  • Support Pseudo Channel mode operation.
  • WRITE Data mask function via CA bus (single/double-byte mask).
  • Supports Data bus inversion (DBI).
  • Supports Command Address bus inversion (CABI).
  • Supports all types of training.
  • Supports Data Mask function.
  • Supports configurable timing parameters and rank associations.
  • Supports capturing all the valid GDDR6 commands including Activate, Read Write, Pre-charge.
  • Supports Power-up Reset and initialization sequences.
  • Supports Power-Down, Self-Refresh & Hibernate Self-Refresh operation.
  • Supports RDQS mode.
  • Supports EDC for both write and read operations.
  • Supports EDC half and full rate.
  • Supports Dynamic Voltage Switching.
  • Supports Temperature sensor.
  • Supports clock to stop, frequency change, and duty cycle corrector.
  • Supports all mode registers configurations.
  • Supports Multi Environment.
  • Reports various timing errors, which can be used to check any timing violations.
  • It provides full control to the user to enable/disable various types of messages.
  • Supports full-timing models or bus functional models.
  • Supports advanced System Verilog features like constrained random testing.
  • Strong Protocol Monitor with real-time exhaustive programmable checks.
  • Supports Dynamic as well as Static Error Injection scenarios.
  • On the fly protocol checking using protocol check functions, static and dynamic assertion.
  • Built-in Coverage analysis.
  • Provides a comprehensive user API (callbacks) in Monitor, Controller, and Memory Model BFMs.
  • Graphical analyzer to show transactions for easy debugging.


  • GDDR6 SDRAM Model
  • GDDR6 Monitor & Scoreboard
  • GDDR6 Memory Controller BFM/Agent
  • Test-Bench Configurations
  • Test Suite (Available in Source code)
    • Basic Protocol Tests
    • Assertions & Cover Point Tests
  • Integration Guide, User Manual, and Release Notes


Download the Product Brochure from here