Truechip's UCIe Verification IP provides an effective & efficient way to verify the UCIe components of an IP or SoC. Truechip's VIP is fully compliant with UCIe Specification version 1.1. The VIP is light weighted with easy plug-andplay components so that there is no hit on the design
Features
Natively maps PCI Express (PCIe 6.0) and Compute Express Link (CXL 2.0, CXL 3.0) protocols.
Supports CXL 2.0 68B Flit Mode, CXL 256B Flit Mode, PCIe 6.0 Flit Mode and Raw Mode for all protocols.
Supports streaming protocol for Raw format.
Supports AXI 3 & 4 Protocols using Raw format.
Supports standard (2D) and Advanced package (2.5D).
Supports single module, two module and four module configuration.
Supports up to 32 GT/s per pin including 4/8/12/16/32 GT/s.
Available with 8/16/32 and 64 lanes.
Supports lane reversal.
Supports lane repair (advanced) and link width degradation (standard).
Supports Flow control and Retry mechanism.
Supports runtime Link Testing through Parity, Scrambling/De-scrambling.
Supports all kind of side-band messages.
Supports LTSM, RDI state machine and FDI state machine.
Supports single and multiple CXL stacks with internal ARB/MUX layer.
Available with in-built UCIe Retimers.
Functional coverage for complete UCIe features.
Monitors, detects and notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
Supports power management across different layers.
Deliverables
Integration Guide, User Manual and Release Notes