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SATA 3.3

Products >> Verification IP >> SATA 3.3

SATA 3.3 Verification IP

Truechip's SATA Verification IP provides an effective & efficient way to verify the components interfacing with SATA interface of an IP or SoC. Truechip's SATA VIP is fully compliant with standard SATA specification. This VIP is a light weight VIP with easy plug-and-play interface so that there is no hit on the design cycle time.

Key Benefits

  • Available in native SystemVerilog(UVM/OVM/ VMM) and Verilog
  • Unique development methodology to ensure highest levels of quality
  • Availability of Compliance & Regression Test Suites
  • 24X5 customer support
  • Unique and customizable licensing models
  • Exhaustive set of assertions and coverage points with connectivity example for all the components
  • Consistency of interface, installation, operation and documentation across all our VIPs
  • Provide complete solution and easy integration in IP and SoC environment 


  • Compliant to SATA 3.3, PIPE and AHCI 1.3.1 Specification and backward Compatible to SATA 1.0 ,SATA 2.0 and SATA 3.2 specification.
  • Supports AHCI functionality on Host (HBA) side.
  • Supports complete functionality of Application, Command, Transport, Link and PHY Layer.
  • Configurable PIPE Interface width 8,16 or 32 bits.
  • Supports PIO, DMA Queued, Device Reset,Execute Device Diagnostics and Non-Data command protocol.
  • Supports Native Command Queuing and FPDMA.
  • Supports DMA Terminate data transmission Functionality
  • Supports BIST FIS transmission and reception and BIST Activate FIS Modes.
  • Supports Automatic FIS retry mechanism.
  • Supports Scrambling and Descrambling.
  • Supports all primitives (ALIGNp, HOLDp, CONTp, SOFp, EOFp, SYNCp, X_RDYp, R_RDYp).
  • Supports Link Transmit,Receive and Power management FSM’s.
  • Supports auto insertion of hold primitive to avoid overflow and underflow.
  • Supports Partial and slumber power management modes.
  • Supports speed negotiation and OOB signaling.
  • Supports advanced SystemVerilog features like constrained random testing.
  • Supports dynamically configurable modes.
  • Strong Protocol Monitor with real time exhaustive programmable checks.
  • Supports Dynamic as well as Static Error Injection scenarios.
  • On the fly protocol checking using protocol check functions, static and dynamic assertion.
  • Built in Extensive Coverage Across the Channels.
  • Provides a comprehensive user API (callbacks) in Command, Transport, Link and PHY layers for user control.
  • Graphical analyser to show transactions for easy debugging.


  • SATA Host/Device BFM for :
    • Phy Layer
    • Link Layer
    • Transport Layer
  • Command Layer and Application Layer
  • SATA Layered Monitor and Scoreboard
  • Test Environment & Test Suite :
    • Basic and Directed Protocol Tests
    • Random Tests
    • Error Scenario Tests
    • Assertions & Cover Point Tests
    • Compliance Tests
  • GUI analyzer for Simulation Packet Flow
  • Integration Guide, User Manual and Release Notes
Download the Product Brochure from here