PIPE Verification IP 

Truechip's PIPE Verification IP provides an effective & efficient way to verify the PIPE components of an IP or SoC. Truechip's VIP is fully compliant with PIPE Specification The VIP is light weight with easy plug-and-play components so that there is no hit on the design cycle time.

Key Benefits

• Available in native System Verilog (UVM/OVM/VMM) and Verilog
• Unique development methodology to ensure the highest levels of quality
• 24X5 customer support
• Unique and customizable licensing models
• Exhaustive set of assertions and coverage points with connectivity examples for all the components
• Consistency of interface, installation, operation, and documentation across all our VIPs
• Provide complete solutions and easy integration in IP and SoC environment

Features

• Utilizes 8-bit, 16-bit, or 32-bit parallel interfaces to transmit and receive PCIe/USB data.
• Support of direct disparity control for use in transmitting compliance patterns.
• 8b/10b encoding and decoding, and error indication (original PIPE).
• 128b/130b encoding and decoding, and error indication (original PIPE).
• Supports Polarity (original PIPE).
• Supports Lane margining at the receiver.
• Supports random reset for all layers of PIPE VIP.
• Functional coverage for complete PIPE features.
• Monitors, detects and notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.

Deliverables

• PIPE Tx/Rx/BFM/Agent
• PIPE Monitor
• PIPE Scoreboard
• Testbench Configurations
• Test Suite (Available in Source code)
  • Basic and Directed Protocol Tests
  • Random Tests and Error Scenario Tests
  • Assertions & Cover Point Tests
• Integration Guide, User Manual and Release Notes