eDP 1.5 Verification IP
Truechip's eDP 1.5 Verification IP provides an effective & efficient way to verify the components interfacing with the eDP interface of an ASIC/FPGA or SoC. Truechip's eDP VIP is fully compliant with Standard eDP Version 1.5 specifications from VESA This VIP is a lightweight VIP with an easy plug-and-play interface so that there is no hit on the design time and the simulation time.
Key Benefits
- Available in native System Verilog (UVM/OVM/ VMM) and Verilog
- Unique development methodology to ensure the highest levels of quality
- Availability of Compliance & Regression Test Suites
- 24X5 customer support
- Unique and customizable licensing models
- Exhaustive set of assertions and coverage points with connectivity examples for all the components
- Consistency of interface, installation, operation, and documentation across all our VIPs
- Provide complete solutions and easy integration in IP and SoC environment
Features
- Fully compliant with VESA Embedded DisplayPort (eDP) Standard 1.5 Specification
- Supports power saving feature:- Panel Self Refresh features PSR/PSR2, PR, Adaptive sync, and backlight control.
- Supports HDCP version 1.4, 2.2 and 2.3
- Supports Alternative Scrambler Seed Reset (ASSR)
- TPS4 with ASSR is supported
- Supports Advanced Link Power Management (ALPM)
- Power Down states (Sleep and Standby)
- Wake state (fast wake timing)
- Supports updated ALPM requirement for DSC in eDP devices
- Supports all standard link rates for eDP
- Supports 1, 2 and 4 lanes of operation on both eDP devices
- Supports Aux Frame Sync for Active Video Timing Synchronization
- Supports GTC-based video timing synchronization
- Supports PSR (Panel Self Refresh) features
- PSR Entry/Exit operation
- Error Management/Recovery mechanism
- Supports PSR2 operations
- Self-refresh with selective updates supported
- PSR2 States has supported
- PSR2 commands and data transport supported
- Supports PSR SDP
- Supports Multi-SST Operations (MSO)
- Multi-SST Operation with Two SST Links,One Lane Each (2x1)
- Multi-SST Operation with Two SST Links, Two Lanes Each (2x2)
- Multi-SST Operation with Four SST Links, One Lane Each (4x1)
- Support for display stream compression
- Supports Display Backlight Control by the way of AUX
- Support transport of Multi-touch data over AUX
- Supports all operations of Main Link , Aux and HPD signalling
- Callback support in BFM to provide user control
- Supports Dynamic as well as Static Error Injection scenarios
- Strong Protocol Monitor with real time exhaustive programmable checks
- Supports dynamically configurable modes
- On-the-fly protocol checking using protocol check functions, static and dynamic assertions
- Built-in Coverage analysis.
- Graphical analyzer to show transactions for easy debugging
Deliverables
- DisplayPort eDP BFM's for:
- Source - Link Layer
- Source - MAC Layer
- Source - PHY Layer
- Sink - Link Layer
- Sink - MAC Layer
- Sink - PHY Layer
- Branching Devices
- DisplayPort layered monitor & scoreboard
- Test Environment & Test Suite:
- Basic and Directed Protocol Tests
- Random Tests
- Error Scenario Tests
- Assertions & Cover Point Tests
- Compliance Test Suite
- User Test Suite
- Integration guide, user manual, and release notes
- GUI analyzer to view simulation packet flow
