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Products >> Verification IP >> JTAG DTM

JTAG DTM Verification IP

Truechip's JTAG DTM Verification IP provides an effective & efficient way to verify the components interfacing with RISC-V Debug Module. It is fully compliant with standard RISC-V Debug Specification 0.13.2 by SiFive, Inc. This VIP is a lightweight VIP with an easy plug-and-play interface so that there is no hit on the design cycle time.

Key Benefits

  • Available in native System Verilog (UVM/OVM/VMM) and verilog
  • Unique development methodology to ensure highest levels of quality
  • Availability of Compliance & Regression Test suites
  • 24X5 customer support
  • Unique and customizable licensing models
  • Exhaustive set of coverage points with connectivity example for all the components
  • Consistency of interface, installation, operation and documentation across all our VIPs
  • Provide complete solution and easy integration in IP and SoC environment


  • Compliant to RISC-V Debug Specification 0.13.2, JTAG DTM provided by SiFive, Inc.
  • Supports all types of JTAG DTM components, master and slave ( TAP ).
  • Wide range of IEEE 1149-1 2013 protocol checks.
  • Configurable Instruction Register Widths ( 5 bits min )
  • Configurable Data Registers ( Variable Widths )
  • User defined instructions ( Bypass, IDCODE, dtmcs, dmi )
  • User defined data register ( IDCODE, dtmcs, dmi )
  • Supports user specific tasks for data loading and reading for on the fly debugging
  • Support for all Test Access Port ( TAP ) pins
  • Basic internal and external clock and reset modes
  • Detailed transaction logs for data comparison and debugging
  • Supports additional analysis port for custom scoreboard implementation
  • Supports programmable data register encodings for use in future implementations
  • Bus assertions for all possible scenarios.
  • Provides detailed statistics for each transaction.
  • Provides a comprehensive user API (callbacks) in all BFMs.


  • JTAG DTM Master/Slave Agent
  • JTAG DTM Bus Monitor, assertion module and Scoreboard.
  • Test Environment and Test Suite:
    • Basic and directed protocol tests.
    • Random Tests.
    • Error Scenario Tests.
    • Assertion and cover-point Tests
    • Integration guide, User Manual, FAQ, and Release Notes.
Download the Product Brochure from here