DFI 6.0 Verification IP
Truechip's Verification IP (VIP) for DFI provides an effective and efficient way to verify the components interfacing with the DFI interface of an ASIC/FPGA or SoC. Truechip's DFI VIP is fully compliant with Standard DFI Specifications. This VIP is a light weight with an easy plug-and-play interface so that there is no hit on the design time and the simulation time.
Key Benefits
- Available in native SystemVerilog (UVM/OVM/VMM) and Verilog.
- Unique development methodology to ensure highest levels of quality.
- 24X5 customer support & response under 90 Min.
- Unique and customisable licensing models.
- Exhaustive set of assertions and cover points with connectivity examples for all the components. Consistency of interface, installation, operation and documentation across all our VIPs.
- Provide a complete solution and easy integration in an IP and SoC environment.
Features
- Compliant with DFI version 2.0, 2.1, 3.0, 3.1, 4.0, 5.0, 5.1, 5.2 & 6.0 specifications.
- DFI Applies to:
- DDR3, DDR4, DDR5, LPDDR3, LPDDR4, LPDDR5, LPDDR6, HBM2E/3, HBM4, GDDR6 and GDDR7 protocols
- Supports all Interface Groups
- Supports below global features:
- Frequency ratios across DFI
- Frequency change
- Low power control
- Error signaling
- PHY-managed interface
- Clock disabling
- Data bit enable
- DFI disconnect
- Independent channel support
- MC to PHY message
- Supports the Memory Topology-specific features.
- Reports various timing errors, which can be used to check any timing violations compliant with DFI 2.0, 2.1, 3.0, 3.1, 4.0, 5.0, 5.1, 5.2 and 6.0 specifications.
- Supports Write Transactions with DBI and Read Transactions with DBI.
- Supports Cyclic Redundancy Check (CRC) on write and read data.
- Supports CA Parity, 2N mode.
- Supports WCK Control.
- Supports CA, CS training.
- Supports write and Read trainings.
- Supports ECC engine test mode of operation
- Provides full control to the user to enable/disable various types of messages.
- Supports full timing models or bus functional models.
- Supports advanced system Verilog features like constrained random testing.
- Strong Protocol Monitor with real-time exhaustive programmable checks.
- Supports Dynamic as well as Static Error Injection scenarios.
- On-the-fly protocol checking using protocol check functions and static and dynamic assertions.
- Built-in coverage analysis
Deliverables
- Memory Model
- Memory Monitor & Scoreboard
- Memory Controller BFM
- DFI PHY BFM model
- DFI Monitor and Scoreboard
- Test-Bench Configurations
- Test Suite (Available in Source Code)
- Basic Protocol Tests
- Directed & Random Tests
- Assertions & Cover Point Tests
- Integration Guide, User Manual and Release Notes
