I3C 1.2 Verification IP

Truechip's I3C Verification IP provides an effective & efficient way to verify the components interfacing with I3C interface of an IP or SoC. Truechip's I3C VIP is fully compliant with Rev. 1.2 of I3C specifications from MIPI. This VIP is a lightweight VIP with easy plug-and-play interface so that there is no hit on the design cycle time.

Key Benefits

• Available in native SystemVerilog (UVM/OVM/VMM) and Verilog
• Unique development methodology to ensure highest level of quality
• Availability of Conformance and Regression Test Suites
• 24x5 customer support
• Unique and customizable licensing models
• Exhaustive set of assertions and cover points with connectivity example for all the components
• Consistency of interface, installation, operation and documentation across all our VIPs
• Provide complete solution and easy integration in IP and SoC environment

Features

• Fully compliant with Rev. 1.2 of the I3C-Bus Specification
• Support existent I2C bus/device. like I2C messaging, Single Data Rate messaging (SDR), etc.
• Support all type of speed modes (SDR + HDR-DDR/HDR-BT/HDR-Ternary).
• Support Broadcast or directed (Common Command Code) command to the target.
• Same controller capable of sending I2C Transfers also.
• VIP's controller BFM can connect to I2C Target Devices.
• Legacy I2C Device co-existence on the same Bus of I3C.
• Dynamic Address allocation.
• In-Band Interrupt support including addition of T-bit at the end of IBI Payload and dependency of MRL values on target.
• Supports protocol-compliant MRL/MWL configuration and reporting, including unrestricted MWL values and handling of unsupported MRL/MWL settings.
• Supports the updated default read value (0x80) for the RSTACT Direct Read CCC, indicating that no reset action is configured.
• Supports conditional ENTDAA CCC handling based on Target Static Address assignment and Hot-Join capability.
• Support Multi Controller and Target
• Can work as secondary controller on request.
• Supports additional Multi-Drop and Hot-Join capability
• Support all type of roles for target (SDR only target and with SDR & HDR mode).
• Supports updated HDR Exit Pattern and the HDR Reset Pattern timings.
• Supports Spike Filter compliance verification for a Target that initially operates as an I²C Target with a Spike Filter enabled.
• Supports GETSTATUS verification for correct indication of pending interrupt status.
• Supports Arbitration and Clock Synchronization.
• Supports generation of transactions with UVM register model.
• Built in I3C Bus Monitor provides extensive protocol checking.
• Supports various error injection and detection.
• Provides verification scalability using functional coverage.
• Provides logging facility for bus traffic in the ASCII format and in user configurable mode.
• Supports timing checks in the Monitor.
• Callbacks for user-defined transfers.
• Supports transaction logging with detailed description of each transfer.
• Graphical analyser to show transactions for easy debugging.

Deliverables

• I3C Controller / Target Agent 
• I3C Monitor and Score board
• Test Environment & Test Suite:
  • Basic and Directed Protocol Tests
  • Random Tests
  • Error Scenario Tests
  • Assertions & Cover Point Tests
• Integration Guide, User Manual and Release Notes