I3C HCI Verification IP (VIP)

Truechip’s I3C HCI Verification IP provides an effective & efficient way to verify the components interfacing with the I3C HCI interface of an IP or SoC. Truechip’s I3C HCI VIP is fully compliant with the MIPI I3C HCI specifications v1.2. This VIP is a lightweight VIP with an easy plug-and-play interface so that there is no hit on the design cycle time.

Key Benefits of I3C HCI VIP

• Available in native SystemVerilog (UVM/OVM/VMM) and Verilog
• Unique development methodology to ensure the highest level of quality
• Availability of Compliance & Regression Test Suites
• 24X5 customer support
• Unique and customizable licensing models
• Exhaustive set of assertions and cover points with connectivity example for all the components
• Consistency of interface, installation, operation and documentation across all our VIPs

Features of I3C HCI VIP

• Fully compliant with I3C HCI v1.2 along with I3C v1.1.1+.
• Maximum 32 Targets can be configured.
• Supports the register interface, data structures and operating modes.
• Supports Legacy I2C and I3C devices, Secondary Master configurations and operations.
•  Supports Managed CCC transfers, including Broadcast CCCs and direct CCCs with NACK retry.
• Supports Dynamic Address Assignment through ENTDAA, plus static and grouped addressing.
• Supports regular I3C SDR transfers, legacy I2C transfers and HDR modes (HDR-DDR, HDR-BT, HDR-TSP, HDR-TSL).
• Supports all types of speed modes.
• Supports additional Multi-Drop and Hot-Join capability
• Supports major In-Band Interrupt features such as immediate data transfers, termination/abort handling, IBI timestamping, flow control, IBI Queue and IBI rings, and automated command processing.
• Supports PIO mode with a Command Queue, Response Queue, Transfer Data port and IBI port, with threshold control and configurable queue sizes.
• Supports DMA mode with up to 8 ring headers, command/response ring pairs, scatter-gather transfers for host system memory.
• Command Queue for software-built command descriptors that detail the bus transfers to execute.
• Response Queue for status flags, error codes and completion markers returned on transfer completion.
• Device Address Table (DAT) tracking each target’s static and dynamic address, IBI configuration and legacy I2C attributes, with parity handling.
• Device Characteristics Table (DCT) storing PID, BCR and DCR values gathered during dynamic address assignment.
• Supports Combo Transfer commands for two-phase operations, such as a write followed by a read through repeated start.
• Verifies ALT_QUEUE_SIZE handling and custom memory partitioning to dynamically tune internal buffer weights, optimizing queue performance for specific workloads.
• Supports Immediate Data transfers and short read-type transfers.
• Supports transfer termination and abort handling in both PIO and DMA modes.
• Supports Scheduled Commands (handler types 1, 2 and 3) for periodic, host-free command execution.
• Supports target reset patterns, bus reset, SDA recovery and Dead Bus Recovery.
• Supports multi-bus instances and the extended capability structure, including vendor-specific capabilities.
• Supports error status codes in response descriptors, with command sequence stall and timeout flows.
• Supports configurable interrupts at the host controller and PIO level, including interrupt force for testing.
• Supports Arbitration and Clock Synchronization.
• Supports various error injection and detection.
• Provides verification scalability using functional coverage.
• Supports timing checks in the Monitor.
• Callbacks for user-defined transfers.
• Supports transaction logging with a detailed description of each transfer.
• Graphical analyzer to show transactions for easy debugging

Deliverables

• I3C HCI Agent
• I3C Controller / Target Agent
• I3C HCI Monitor
• I3C scoreboard
• Test environment and test suite
  • Basic and directed protocol tests
  • Random Tests
  • Error Scenario Tests
  • Assertions & Cover Point Tests
• Integration Guide, User Manual and Release Notes