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- FE Verification
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- Analog Characterization
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| Please email your CV to careers@truechip.net with the Job ID in the subject field. |
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Details for Job ID: IC-DV01
| Design Engineer |
: 2 to 4 yrs |
| Location |
: Delhi-NCR or Bangalore |
| Openings |
: 20 |
| Education |
:BE/B.Tech./MS/M.Tech.(Electronics or Electronics & Communication) |
Core Competencies:
- Worked on SoC level testbench and verification environment
- Testbench architecture, coding and good understanding of design issues in RTL
- Testbench generation, testvector creation, simulations, gate level simulations
- Hands on with System Verilog and Assertion based verification methodology
- Atleast 2years of experience on HVL (System Verilog, Vera, Specman, E, VMM, OVM, UVM)
Simulation Tools: NCSIM/VCS/ModelSim/Questa
Added Advantage:
- Knowledge of RTL coding styles
- Low power verification (UPF/CPF) would be an added plus
- Experience on System C would be an added plus
- Worked on protocols like AMBA AHB/AXI, MIPI, PCI Express, SATA, USB
Email you resume to careers@truechip.netand mention position/location in the subject
Details for Job ID: IC-DV02
| Sr. Design Engineer |
: 4 to 6 yrs |
| Location |
: Delhi-NCR or Bangalore |
| Openings |
: 12 |
| Education |
: BE/B.Tech./MS/M.Tech. (Electronics or Electronics & Communication) |
Core Competencies:
- Worked on SoC level testbench and verification environment
- Testbench architecture, coding and good understanding of design issues in RTL
- Testbench generation, testvector creation, simulations, gate level simulations
- Hands on with System Verilog and Assertion based verification methodology
- Atleast 2years of experience on HVL (System Verilog, Vera, Specman, E, VMM, OVM, UVM)
- Should be able to work independently and able to guide others
Simulation Tools: NCSIM/VCS/ModelSim/Questa
Added Advantage:
- Knowledge of RTL coding styles
- Low power verification (UPF/CPF) would be an added plus
- Experience on System C would be an added plus
- Worked on protocols like AMBA AHB/AXI, MIPI, PCI Express, SATA, USB
Email you resume to careers@truechip.netand mention position/location in the subject
Details for Job ID: IC-DV03
| Lead Engineer |
: 6 to 9 yrs |
| Location |
: Delhi-NCR or Bangalore |
| Openings |
: 8 |
| Education |
: BE/B.Tech./MS/M.Tech. (Electronics or Electronics & Communication) |
Core Competencies:
- Worked on SoC level testbench and verification environment
- Testbench architecture, coding and good understanding of design issues in RTL
- Testbench generation, testvector creation, simulations, gate level simulations
- Hands on with System Verilog and Assertion based verification methodology
- Atleast 3years of experience on HVL (System Verilog, Vera, Specman, E, VMM, OVM, UVM)
- Should be able to work independently and able to guide other team members
- Should be able to lead a team of 5-10 engineers.
Simulation Tools: NCSIM/VCS/ModelSim/Questa
Added Advantage:
- Knowledge of RTL coding styles
- Low power verification (UPF/CPF) would be an added plus
- Experience on System C would be an added plus
- Worked on protocols like AMBA AHB/AXI, MIPI, PCI Express, SATA, USB
Email you resume to careers@truechip.netand mention position/location in the subject
Details for Job ID: IC-DV04
| Design Manager |
: 8 yrs |
| Location |
: Delhi-NCR or Bangalore |
| Openings |
: 4 |
| Education |
: BE/B.Tech./MS/M.Tech. (Electronics or Electronics & Communication) |
Core Competencies:
- Worked on SoC level testbench and verification environment
- Testbench architecture, coding and good understanding of design issues in RTL
- Testbench generation, testvector creation, simulations, gate level simulations
- Hands on with System Verilog and Assertion based verification methodology
- Atleast 4years of experience on HVL (System Verilog, Vera, Specman, E, VMM, OVM, UVM)
- Should be able to work independently and able to guide other team members
- Problem solving capabilities with leadership qualities
- Should have managed a team of 10 or more engineers
Simulation Tools: NCSIM/VCS/ModelSim/Questa
Added Advantage:
- Knowledge of RTL coding styles
- Low power verification (UPF/CPF) would be an added plus
- Experience on System C would be an added plus
- Worked on protocols like AMBA AHB/AXI, MIPI, PCI Express, SATA, USB
Email you resume to careers@truechip.netand mention position/location in the subject |
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Details for Job ID: IC-DFT01
| Relevant Exp level |
: 3 to 5 yrs |
| Location |
: Delhi-NCR or Bangalore |
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| Education |
: BE/ BTech (Electronics/ Electrical/ Electronics and Communication)
MS or MTech would be preferred |
The candidate is expected to have worked on :
- Scan insertion and DRC cleanup
- Pattern generation for Stuck-At, delay test, iddq, path delay and fault grading.
- Memory testing. Should also know the algorithms. Should also have knowledge about diagnostics.
- JTAG or P1500 or other interface mechanism
Desirable competencies
The candidate is expected to have exposure to :
- Compression tools is highly desirable
- LBIST, mixed-signal testing, logic equivalence
- Writing testbenches and should be capable of writing RTL code for DFT blocks as and when required.
- Bridge fault detection is desirable
- ATE experience is an added advantage |
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Details for Job ID: IC-DFT02
| Relevant Exp level |
: 5 to 7 yrs |
| Location |
: Delhi-NCR or Bangalore |
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| Education |
: BE/ BTech (Electronics/ Electrical/ Electronics and Communication)
MS or MTech would be preferred |
Core competencies:
The candidate should have :
- Led a DFT team for at least two SOCs
- A hold over the complete flow i.e. scan, atpg, structures for delay test,
coverage analysis, memory testing, netlist simulations and pattern delivery.
- Ability to decide on the take decision on approaches
- Ability to decide on the the schedule and effects on it due to different approaches.
- Exposure to LBIST, mixed-signal testing and post-silcon bring up
- Exposure to timing or synthesis and should be able to decide on the constraints for the same.
- Ability to mentor the junior team members and drive them for achieving best results.
- Ability to communicate and discuss options with the client. |
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Details for Job ID: IC-AV01
| Job Profile |
: Silicon Validation of Analog IP in SOC |
| Relevant Exp level |
: 4 to 8 yrs |
| Location |
: Delhi-NCR or Bangalore |
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| Education |
: BE/ BTech (Electronics/ Electrical/ Electronics & Comm)
: MSc (VLSI/ Electronics/ Electrical/ Electronics & Comm)
: MS or MTech would be preferred |
Core Competencies:
- VLSI Testing - Post Silicon Validation of 22nm, 32nm, 45nm, 65nm and 90nm Analog IPs
- Programming Languages: LABVIEW, C, C++, Assembly
- Candidate should be able to setup LabVIEW based automation for Post Silicon Validation
- Signal Integrity Analysis using Agilent-ADS and/ or Cadence - Allegro PCB designer
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Candidate should have defined, developed and executed Test Plans for Analog Electrical Characterization of advanced
CMOS I/O’s, Compensation blocks, DDR, BIDIRS, LVDS, PLL, Power Management Block, LDO, ADC, etc.
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Perform Analog electrical characterization, Signal measurements with the ATE
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Familiarity with High BW Oscilloscope, Pattern & Pulse Generator, Time Domain Reflectometry, Eye Analysis |
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