Design Verification
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Functional Verification Ethernet Verification IP

Lead RTL

RTL >> Lead RTL
  • Post:
  • Lead RTL
  • Required Experience:
  • 6 to 10 Years
  • Location:
  • Bangalore, Delhi NCR, Hyderabad
  • Openings
  • 8-10
  • Education
  • BE/B.Tech./MS/M.Tech.(Electronics or Electronics & Communication)

Key Responsibilities-
  • Pre-Silicon validation platform development
  • Porting of SoC/IP RTL for FPGA implementation
  • Development and execution of system use case scenarios
  • Ability to work well as part of a team
  • min 6-8 years of experience in FPGA platform development and/or validation of IP/SS on FPGA
  • Should be able to understand system level environment
  • Planning Test strategy, creating test plan and test code development to address functional and performance requirements of the IP/Subsystem.
  • Experience with HDL languages (Verilog/systemverilog and VHDL) and/or working knowledge of C/C++ is a must.
  • Expertise in using compiler and debugging tools like GHS, Lauterbach
  • HW debugging skills, FPGA debugging using chipscope etc.
  • Expertise in using validation environment test equipment e.g. Logic Analyzers, Oscilloscope, Protocol Analyzers etc.
  • Experience in working on ARM core architectures would be an advantage.
  • Exposure to Xilinx Ultrascale device architecture and designing for the device will be an advantage.