Design Verification
loading...
Thank you for your query. We will reply to you at the earliest.
Functional Verification Ethernet Verification IP

CXL

Products >> Verification IP >> CXL

CXL Verification IP

Truechip's CXL Verification IP provides an effective & efficient way to verify the components interfacing with CXL interface of an IP or SoC.

Truechip's CXL VIP is fully compliant with latest CXL specifications. This VIP is a light weight with an easy plug-and-play interface so that there is no hit on the design cycle time.

Features

  • Compliant with the CXL 1.1 specification.
  • Verification IP configurable as CXL Host and Device when operating in Flex Bus mode and as PCI Express Root Complex and Device Endpoint when operating in PCIe mode.
  • Support for all three CXL protocols i.e., CXL.io, CXL.cache, CXL.mem and device types to meet specific application requirements with user configurable memory size for both CXL Host and Device.
  • Support for CXL Downstream and CXL Upstream Port registers (located at RCRB and MEMBAR0).
  • Support for 32.0 GT/s Data Rate with backward compatibility.
  • Support for Alternate Protocol Negotiation for CXL Mode.
  • Support Pipe Specification 5.1 with both Low Pin Count and Serdes Architecture.
  • Support for ARB/MUX for CXL ALMP transmission and reception to control virtual link state machine and power state transition requests.
  • Support for CXL ACK forcing and Link Layer Credit exchange mechanism.
  • Support Arbitration among the CXL.IO,CXL.cache and CXL.mem packets with Interleaving of traffic between different CXL protocols.
  • Support for randomization and user controllability in flit packing.
  • Support for CXL Link Layer Retry Mechanism.
  • Support for Configurable timeout for all three layers.
  • Support for different CXL/PCIe Resets.
  • Support for power management including the low power L1 with sub-state and L2.
  • Support for x1,x2,x4,x8 & x16 Lanes.
  • Provides a comprehensive user API (callbacks).
  • Graphical analyser for all CXL/PCIE layers(Transaction Layer, Link Layer and Phy Layer) along with CXL ARB MUX to show transactions for easy debugging.
  • Built in Coverage analysis.

Deliverables

  • CXL Host/Device
  • CXL BFM/Agents for:
    • l Host and Device sequences
    • l Transaction layer(CXL.IO and CXL.cache, CXL.mem)
    • l Link layer(CXL.IO and CXL.cache, CXL.mem)
    • l Arbiter/Mux layer
    • l Phy layer
  • CXL Monitor and Scoreboard
  • Test Environment & Test Suite:
    • l Basic and Directed Tests
    • l Random Tests
    • l Error Injection Tests
    • l Assertion and Cover point Tests
    • l Compliance Tests
  • Integration Guide, User Manual and Release Notes

Key Benefits

  • Available in native SystemVerilog (UVM/OVM/VMM) and Verilog
  • Unique development methodology to ensure highest levels of quality
  • 24X5 customer support
  • Unique and customizable licensing models
  • Exhaustive set of assertions and cover points with connectivity example for all the components
  • Consistency of interface, installation, operation and documentation across all our VIPs
  • Provide complete solution and easy integration in IP and SoC environment.​

 

 

 

 

Download the Product Brochure from here