Design Verification
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Functional Verification Ethernet Verification IP

DDR4/3

Products >> Verification IP >> DDR4/3

DDR4 Verification IP

Truechip's DDR4 Verification IP provides an effective & efficient way to verify the components interfacing with DDR4 interface of an ASIC/FPGA or SoC. Truechip's DDR4 VIP is fully compliant with Standard DDR4 Version JESD79-4B specification from JEDEC. This VIP is a lightweight with an easy plug-and-play interface so that there is no hit on the design time and the simulation time.

Key Benefits  

  • Available in native SystemVerilog(UVM/OVM/VMM) and Verilog
  • Unique development methodology to ensure the highest levels of quality
  • Availability of various Regression Test Suites
  • 24X5 customer support
  • Unique and customizable licensing models
  • Exhaustive set of assertions and cover points with connectivity example for all the components
  • Consistency of interface, installation, operation, and documentation across all our VIPs
  • Provide complete solution and easy integration in IP and SoC environment.

Features

  • Compliant to JEDEC DDR4 SDRAM Specification version JESD79-4B.
  • Supports connection to any DDR4 Memory Controller IP communicating with a JESD79-4B compliant DDR4 Memory Model.
  • Supports configurable SDRAM addressing of different sizes (x4,x8 and x16).
  • Available in all memory sizes from 2 Gb to 16 Gb.
  • Support for all speed-grades/speed-bins.
  • 3DS Memory Model also available.
  • Supports all burst length i.e BL8, BC4.
  • Supports Data Bus Inversion (DBI).
  • Supports Data Masking (DM).
  • Supports CAL mode (CS_n to command address latency).
  • Supports capturing all the valid DDR4 commands including Activate, Read Write, Precharge.
  • Supports all trainings i.e write leveling, DQ training from MPR, Read preamble training.
  • Supports reading and writing from MPR in all modes i.e serial, parallel, staggered.
  • Supports CA parity for command/address bus.
  • Supports Power-up Reset and initialization sequences.
  • Supports write CRC correction and error detection.
  • Supports Precharge Power-Down, Active Power-Down, Self-Refresh operation.
  • Supports maximum power saving mode.
  • Supports Refresh i.e postpone refresh, pull-in refresh.
  • Supports Connectivity Test Mode.
  • Supports Per DRAM Addressability.
  • Supports Post Package repair.
  • Supports configurable timing parameters and rank associations.
  • Reports various timing errors, which can be used to check any timing violations.
  • Provides full control to the user to enable / disable various types of messages.
  • Supports full timing models or bus functional models.
  • Support for Multiple Ranks architecture.
  • Supports advanced SystemVerilog features like constrained random testing.
  • Supports dynamically configurable modes.
  • Strong Protocol Monitor with real time exhaustive programmable checks.
  • Supports Dynamic as well as Static Error Injection scenarios.
  • On the fly protocol checking using protocol check functions, static and dynamic assertion.
  • Built in Coverage analysis.
  • Provides a comprehensive user API (callbacks) in Monitor, Controller and Memory Model BFMs.
  • Graphical analyzer to show transactions for easy debugging i.e TRUEYE.​
  • Supports RCD, DB, RDIMM and LRDIMM.

Deliverables

  • DDR4-SDRAM Model
  • DDR4 Monitor & Scoreboard
  • DDR4 Memory Controller BFM/Agent
  • DDR4 PHY BFM model
  • DDR4 Phy Monitor and Scoreboard
  • Test-Bench Configurations
  • Test Suite (Available in Source code)
  • Basic Protocol Tests
  • Directed & Random Tests  
  • Assertions & Cover Point Tests
  • Integration Guide, User Manual and Release Notes
Download the Product Brochure from here