Ethernet 25G, 50G Verification IP
Truechip’s 25G/50G Ethernet Verification IP provides an effective & efficient way to verify the components interfacing with Ethernet interface of an IP or SoC. Truechip’s 25G/50G Ethernet VIP is fully compliant with IEEE standard 802.3 specification and 25G‐50G specification revision 2.0. This VIP is a light weight VIP with easy plug‐and‐ play interface so that there is no hit on the design cycle time.
Features
- Provides 25/50 Gb/s as per IEEE std 802.3 and 25G‐50G specification revision 2.0,
- Supports XGMII for 25G and XLGMII for 50G
- Supports 25G BASE‐ KR1/ 25G BASE‐ Cr1
- Supports 50G BASE‐ KR2/ 50G BASE‐ Cr2
- Supports BASE‐R FEC and Reed Solomon FEC
- One lane PCS for 25G BASE‐R (clause 49)
- Four lane PCS for 50G BASE‐R (clause 82)
- Supports Auto negotiation for link speed negotiation
- Supports Energy Efficient Ethernet.
- Supports clock data recovery(CDR).
- Supports Pause Frame Based Flow Control.
- Supports test pattern generation and checking.
- Supports Management data Input/output registers.
- Supports full duplex operation.
- Supports AM insertion in 25G PCS to connect to Reed Solomon FEC.
- Call backs support in all Layers to provide user control.
- Rich set of configuration and parameters.
- Supports Dynamic as well as Static Error Injection scenarios.
- On the fly protocol checking
- Static and dynamic assertion.
- Built in Coverage analysis.
- Graphical analyzer to show transactions for easy debugging.
Deliverables
- MAC layer
- Reconciliation layer
- PCS layer
- BASE‐R FEC layer
- Reed Solomon FEC layer
- PMA layer
- PMD layer
- AN layer
- Ethernet 25G/50G layered monitors and scoreboard
- Test environment and Test Suite‐
- Basic Tests
- Error injection tests
- Assertions & Cover Point Tests
- Integration Guide, User Manual and Release Note
- GUI analyser to view simulation packet Flow
