HBM3E Verification IP

Truechip's HBM3E Verification IP provides an effective & efficient way to verify the components interfacing with HBM interface of an ASIC/FPGA or SoC. Truechip's HBM3E VIP is fully compliant with Standard HBM Version JESD238A specifications from JEDEC. This VIP is a light weight VIP with easy plug-and-play interface so that there is no hit on the design time and the simulation time.

Key Benefits

• Available in native SystemVerilog (UVM/OVM/VMM) and Verilog.
• Unique development methodology to ensure highest levels of quality.
•  Availability of Compliance & Regression Test Suites
• 24X5 customer support.
• Unique and customizable licensing models.
• Exhaustive set of assertions and cover points with connectivity example for all the components.
• Consistency of interface, installation, operation and documentation across all our VIPs.
• Provide complete solution and easy integration in IP and SoC environment.

Features

• Compliant to JEDEC HBM3 SDRAM Specification version JESD238A
• Supports connection to any HBM Memory Controller IP communicating with a JESD238A compliant HBM Memory Model
• Reports various timing error signals, which can be used to check for any timing errors
• Provides full control to the user to enable/disable various types of messages
• Integrates easily in any verification environment
• Supports full timing models or bus functional models
• Multiple instances of Monitor can be instantiated in a Verification Environment to support multiple Stacks
• Supports advanced System Verilog features like constrained random testing
• Supports Callback / User Configuration in Monitor, Controller and Memory Model BFMs
• Supports a wide variety of Error Injection scenarios
• Supports Independent channel functioning
• Available in all Stack memory sizes (16 Channels / Stack): 8 Gb, 16Gb, 24Gb and 32Gb, with configurations of 8-High, 12-High or 16-High, & compatible with 36Gb 8-High or 48Gb 12-High configurations
• Available in Channel Density of 2Gb, 4 Gb, 6Gb and 8Gb
• Data-Bus width: 1024 (64 DQ width/per Channel)
• Support Up to 16 channels/device
• Support 16, 32, 48, or 64 banks per channel
• Supports Data Bus Inversion (DBIac) Feature
• Supports Parity Checking for Command/Address bus & Data bus
• Supports configurable timing parameters & Channels-Die associations
• Supports capturing all the valid HBM Row & Column commands including Activate, Read, Write, Pre charge, Refresh in semi-independent way
• Supports Power-up Reset and initialization sequences
• Supports Power-Down, Self-Refresh operation
• Support Refresh Management, Adaptive Refresh Management
• Support Round rules for Row Access Timing
• Support On-die Dram ECC
• Support WDQS-to-CK Alignment Training, DCA/DCM Training
• Supports Loopback Test Mode
• Supports IEEE testport feature

Deliverables

• HBM Controller BFM
• HBM DRAM
• HBM Monitor and Scoreboard
• HBM PHY BFM Model
• HBM PHY Monitor and Scoreboard
• Test Environment & Test Suites
• Test Suite (Available in Source code)
  • Basic and Directed Protocol Tests
  • Random Tests and
  • Error Scenario Tests
  • Assertions & Cover Point Tests
• Integration Guide, User Manual and Release Notes