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Functional Verification Ethernet Verification IP

LPDDR4/3

Products >> Verification IP >> LPDDR4/3

LPDDR4 Verification IP

Truechip's LPDDR4 Verification IP provides an effective & efficient way to verify the components interfacing with LPDDR4 interface of an ASIC/FPGA or SoC.

Truechip's LPDDR4 VIP is fully compliant with Standard LPDDR4 Version JESD209-4B specifications from JEDEC. This VIP is a light weight VIP with easy plug-and-play interface so that there is no hit on the design time and the simulation time. 

Key Benefit

  • Available in native System Verilog (UVM/OVM/VMM) and Verilog 
  • Unique development methodology to ensure highest levels of quality
  • Availability of various Regression Test Suites 24X5 customer support
  • Unique and customizable licensing models
  • Exhaustive set of assertions and coverage points with connectivity example for all the components 
  • Consistency of interface, installation, operation and documentation across all our VIPs 
  • Provide complete solution and easy integration in IP and SoC environment 

Features

  • Compliant to JEDEC LPDDR4 Specification version JESD209-4B. 
  • Supports LPDDR4 memory devices from all leading vendors. 
  • Supports multiple densities: 4Gb to 32Gb. 
  • Supports capturing of all the valid LPDDR4 commands as per the specs. 
  • Supports dual channels which can function independently. 
  • Supports Data Bus Inversion and Data Masking(DM).
  • Support for all speed-grades/speed-bins.
  • Support for Multiple Ranks architecture.
  • Constantly monitors LPDDR4 behavior during simulation. 
  • Supports Programmable READ/WRITE Latency timings. 
  • Supports programming of All Mode Registers.
  • Support CA training and DQ calibration.
  • Support write data mask and data strobe features.
  • Support for Power Down features. 
  • Support for full-timing as well as behavioral versions in one model. 
  • Support for all timing delay ranges in one model: min and max. 
  • Reports various timing errors, which can be used to check any timing violations. 
  • Provides full control to the user to enable / disable various types of messages.
  • Supports advanced SystemVerilog features like constrained random testing. 
  • Supports dynamically configurable modes.
  • Strong Protocol Monitor with real time exhaustive programmable checks.
  • Supports Dynamic as well as Static Error Injection scenarios.
  • On the fly protocol checking using protocol check functions, static and dynamic assertion. 
  • Built in Coverage analysis.
  • Provides a comprehensive user API (callbacks) in Monitor, Controller and Memory Model BFMs. 
  • Graphical analyser to show transactions for easy debugging.

Deliverables

  • LPDDR4-SDRAM Model
  • LPDDR4 Monitor and Scoreboard
  • LPDDR4 Memory Controller BFM/Agent 
  • LPDDR4 PHY BFM model 
  • LPDDR4 Phy Monitor and Scoreboard
  • Test-Bench Configurations 
  • Test Suite (Available in Source code) :
    • Basic Protocol Tests
    • Directed & Random Tests
    • Assertion and Cover Point Tests
  • Integration Guide, User Manual and Release Notes
  • GUI analyser to view simulation packet Flow

LPDDR3  Verification IP

 

Truechip's LPDDR3 Verification IP provides an effective & efficient way to verify the components interfacing with LPDDR3 interface of an ASIC/FPGA or SoC.

Truechip's LPDDR3 VIP is fully compliant with Standard LPDDR3 Version JESD209-3C specifications from JEDEC. This VIP is a light weight VIP with easy plug-and-play interface so that there is no hit on the design time and the simulation time.

Key Benefits  

  • Available in native SystemVerilog (UVM/OVM/VMM) and Verilog    
  • Unique development methodology to ensure highest levels of quality
  • Availability of various Regression Test Suites 
  • 24X5 customer support 
  • Unique and customizable licensing models 
  • Exhaustive set of assertions and cover points with connectivity example for all the components 
  • Consistency of interface, installation, operation and documentation across all our VIPs 
  • Provide complete solution and easy integration in IP and SoC environment

Features

  • Supports LPDDR3 memory devices from all leading vendors. 
  • Compliant to JEDEC LPDDR3 Specification version JESD209-3C. 
  • 4Gb to 32Gb densities , x16 and x32 wide data bus 
  • Partial Array Self Refresh, ZQ Calibration, CA training, DQ Calibration
  • Deep Power Down, Power Down, Write leveling, Data Mask. 
  • Supports all Speed Grades.
  • Supports programming of all Mode Registers. 
  • Constantly monitors LPDDR3 behavior during simulation. 
  • Support for full-timing as well as behavioral versions in one model. 
  • Support for all timing delay ranges in one model: min, typical and max.
  • Reports various timing error signals used to check timing violations. 
  • Provides full control to the user to enable / disable various types of messages.
  • Supports full timing models or bus functional models.
  • Supports advanced SystemVerilog features like constrained random testing.
  • Supports dynamically configurable modes.
  • Strong Protocol Monitor with real time exhaustive programmable checks.
  • Supports Dynamic as well as Static Error Injection scenarios.
  • On the fly protocol checking using protocol check functions, static and dynamic assertion.
  • Built in Coverage analysis.
  • Provides a comprehensive user API (callbacks) in Monitor, Controller and Memory Model BFMs.
  • Graphical analyzer to show transactions for easy debugging.

Deliverables

  • LPDDR3-SDRAM Model
  • LPDDR3 Monitor and Scoreboard 
  • LPDDR3 Memory Controller BFM/Agent
  • LPDDR3 PHY BFM mode
  • LPDDR3 PHY Monitor and Scoreboard 
  • Test-Bench Configurations
  • Test Suite (Available in Source code) :
    • Basic Protocol Tests         
    • Directed & Random Tests   
    • Assertion and Cover Point Tests
  • Integration Guide, User Manual and Release Notes
  • GUI analyser to view simulation packet Flow

 

Download the Product Brochure from here