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LPDDR5 / 5x

Products >> Verification IP >> LPDDR5 / 5x

LPDDR5 Verification IP

Truechip's LPDDR5 Verification IP provides an effective & efficient way to verify the components interfacing with LPDDR5 interface of an ASIC/FPGA or SoC. Truechip's LPDDR5 VIP is fully compliant with Standard LPDDR5 specifications from JEDEC. This VIP is a lightweight VIP with an easy plug-and-play interface so that there is no hit on the design time and the simulation time.

Key Benefits

  • Available in native System Verilog (UVM/OVM/VMM) and Verilog
  • Unique development methodology to ensure highest levels of quality
  • Availability of various Regression Test Suites
  • 24X5 customer support
  • Unique and customizable licensing models
  • Exhaustive set of assertions and cover points with connectivity example for all the components
  • Consistency of interface, installation, operation, and documentation across all our VIPs
  • Provide complete solution and easy integration in IP and SoC environment


  • Compliant to JEDEC LPDDR5 Specification.
  • Supports LPDDR5 memory devices from all leading vendors.
  • Supports all memory densities up to 32 Gb per channel.
  • Supports X8, byte mod, and X16 device modes.
  • Supports all burst lengths.
  • Supports capturing of all the valid LPDDR5 commands as per the specs.
  • Supports Data Bus Inversion and Data Masking (DM).
  • Support for all speed-grades/speed-bins.
  • Constantly monitors LPDDR5 behavior during simulation.
  • Supports Programmable READ/WRITE Latency timings.
  • Supports programming of All-Mode Registers.
  • Support CA Bus, WCK2CK, Read DQ, and WCK-DQ training.
  • Support CAS WR, CAS RD, CAS FS, WCK free-running mode, and CAS off.
  • Supports BG, 8B, and 16B modes and dynamically switches between them.
  • Supports CKR=2 and CKR=4.
  • Supports single-ended clocks, frequency change, and clock stop.
  • Supports refresh, postpone, and pull in of refresh, SRE, PASR, sleep mode, SR power down, and DSM modes.
  • Supports data copy and WRX operations.
  • Supports PPR and TRR.
  • Supports ECC for write and read.
  • Supports ZQ, MPC, DCM and DCA, and WCK2CK oscillator.
  • Supports DVFSC, DVFSQ, ODT, thermal sensor, and temperature offset.
  • Support for Power Down features.
  • Supports RDQS, RDQS toggle mode, and enhanced RDQS mode.
  • Supports all WCK and RDQS preamble and postamble patterns.
  • Support for full-timing as well as behavioral versions in one model.
  • Support for all timing delay ranges in one model: min and max.
  • Reports various timing errors, which can be used to check any timing violations.
  • It provides full control to the user to enable/disable various types of messages.
  • Supports advanced System Verilog features like constrained random testing.
  • Supports dynamically configurable modes.
  • Strong Protocol Monitor with real-time exhaustive programmable checks.
  • Supports Dynamic as well as Static Error Injection scenarios.
  • On the fly protocol checking using protocol check functions, static and dynamic assertion.
  • Built-in Coverage analysis.
  • Provides a comprehensive user API (callbacks) in Monitor, Controller, and Memory Model BFMs.
  • Graphical analyzer to show transactions for easy debugging


  • LPDDR5-SDRAM Model
  • LPDDR5 Monitor and Scoreboard
  • LPDDR5 Memory Controller BFM/Agent
  • LPDDR5 PHY BFM model
  • LPDDR5 DFI Monitor and DFI Scoreboard
  • Test-Bench Configurations
  • Test Suite (Available in Source code) :
    • Basic Protocol Tests
    • Directed & Random Tests
    • Assertion and Cover Point Tests
  • Integration Guide, User Manual, and Release Notes
  • GUI analyzer to view simulation packet Flow
Download the Product Brochure from here