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Functional Verification Ethernet Verification IP

LPDDR5

Products >> Verification IP >> LPDDR5

LPDDR5 Verification IP

Truechip's LPDDR5 Verification IP provides an effective & efficient way to verify the components interfacing with LPDDR5 interface of an ASIC/FPGA or SoC.​

Truechip's LPDDR5 VIP is fully compliant with Standard LPDDR5 specifications from JEDEC. This VIP is a light weight VIP with easy plug-and-play interface so that there is no hit on the design time and the simulation time.

Key Benefits

  • Available in native System Verilog (UVM/OVM/VMM) and Verilog​
  • Unique development methodology to ensure highest levels of quality
  • Availability of various Regression Test Suites
  • 24X5 customer support
  • Unique and customizable licensing models
  • Exhaustive set of assertions and cover points with connectivity example for all the components
  • Consistency of interface, installation, operation and documentation across all our VIPs
  • Provide complete solution and easy integration in IP and SoC environment

Features

  • Compliant to JEDEC LPDDR5 Specification.
  • Supports LPDDR5 memory devices from all leading vendors.
  • Supports all memory densities upto 32 Gb per channel.
  • Supports X8 and X16 device modes.
  • Supports all burst lengths.
  • Supports capturing of all the valid LPDDR5 commands as per the specs.
  • Supports Data Bus Inversion and Data Masking (DM).
  • Support for all speed-grades/speed-bins.
  • Constantly monitors LPDDR5 behavior during simulation.
  • Supports Programmable READ/WRITE Latency timings.
  • Supports programming of All Mode Registers.
  • Support CA Bus training.
  • Support for Power Down features.
  • Support for full-timing as well as behavioral versions in one model.
  • Support for all timing delay ranges in one model: min and max.
  • Reports various timing errors, which can be used to check any timing violations.
  • Provides full control to the user to enable / disable various types of messages.
  • Supports advanced System Verilog features like constrained random testing.
  • Supports dynamically configurable modes.
  • Strong Protocol Monitor with real time exhaustive programmable checks.
  • Supports Dynamic as well as Static Error Injection scenarios.
  • On the fly protocol checking using protocol check functions, static and dynamic assertion.
  • Built in Coverage analysis.
  • Provides a comprehensive user API (callbacks) in Monitor, Controller and Memory Model BFMs.
  • Graphical analyzer to show transactions for easy debugging.

Deliverables

  • LPDDR5-SDRAM Model
  • L PDDR5 Monitor and Scoreboard
  • L PDDR5 Memory Controller BFM/Agent
  • L PDDR5 PHY BFM model
  • L PDDR5 DFI Monitor and DFI Scoreboard
  • T est-Bench Configurations
  • T est Suite (Available in Source code) :
    • Basic Protocol Tests
    • Directed & Random Tests
    • Assertion and Cover Point Tests
  • Integration Guide, User Manual and Release Notes
  • GUI analyser to view simulation packet Flow
Download the Product Brochure from here