Design Verification
loading...
Thank you for your query. We will reply to you at the earliest.
Functional Verification Ethernet Verification IP

QSPI/UART

Products >> Verification IP >> QSPI/UART

QSPI Verification IP

Truechip's QSPI Verification IP provides an effective & efficient way to verify the components interfacing with SPI interface of an ASIC/FPGA or SoC.

Truechip's QSPI VIP is fully compliant with Motorola S12SP1V3/D SPI Block Guide V03.06 specification. This VIP is a light weight with an easy plug-and-play interface so that there is no hit on the design time and the simulation time.

Key Benefits

  • Available in native SystemVerilog (UVM/OVM/VMM) and Verilog
  • Unique development methodology to ensure highest level of quality
  • Availability of Compliance & Regression Test Suites
  • 24X5 customer support
  • Unique and customizable licensing models
  • Exhaustive set of assertions and cover points with connectivity example for all the components
  • Consistency of interface, installation, operation and documentation across all our VIPs

Features

  • Supports Motorola S12SP1V3/D SPI Block Guide V03.06
  • Master and Slave Configurations
  • All SPI operating modes
  • Separate control of changing the length of instruction, address and data phase in case of write and Command/Address/Dummy phase/Data in case of read.
  • Data rate control from master agent.
  • Supports single, dual and quad mode bus width operation.
  • Bit and Byte Endianness.
  • Supports Callback / User Configuration in Monitor, Master and Slave BFMs for modifying, and sampling data/command on SPI bus.
  • Complete regression suite containing all the SPI testcases.
  • Examples showing how to connect various components, and usage of Master, Slave and Monitor.
  • Provides full control to the user to enable / disable various types of messages.
  • Supports out-of-box testing.
  • Built in Coverage analysis
  • Supports advanced System Verilog features like constrained random testing.
  • Supports wide variety of Dynamic as well as Static Error Injection scenarios.
  • Detailed documentation of all class, task and function's used in verification env.

Deliverables

  • Quad SPI Slave BFM
  • Quad SPI Monitor & Scoreboard
  • Quad SPI Mater BFM/Agent
  • Test-Bench Configurations
  • Test Suite (Available in Source code)
    • Basic Protocol Tests
    • Directed & Random Tests
    • Assertions & Cover Point Tests
    • Error Scenarios Tests
  • Integration Guide, User Manual and Release Notes
Download the Product Brochure from here