UCIe Verification IP

Truechip's UCIe Verification IP provides an effective & efficient way to verify the UCIe components of an IP or SoC. Truechip's VIP is fully compliant with UCIe Specification version 1.0. The VIP is light weight with easy plug-and-play components so that there is no hit on the design cycle time.

Key Benefits

• Available in native SystemVerilog (UVM/OVM /VMM) and Verilog
• Unique development methodology to ensure highest levels of quality
• Availability of various Regression Test Suites
• 24X5 customer support
• Unique and customizable licensing models
• Exhaustive set of assertions and cover points with connectivity example for all the components
• Consistency of interface, installation, operation and documentation across all our VIPs
• Provide complete solution and easy integration in IP and SoC environment.

Features

• Natively maps PCI Express (PCIe 6.0) and Compute Express Link (CXL 2.0, CXL 3.0) protocols.
• Supports CXL 2.0 68B Flit Mode, CXL 256B Flit Mode, PCIe 6.0 Flit Mode and Raw Mode for all protocols.
• Supports standard (2D) and Advanced package (2.5D).
• Supports single module, two module and four module configuration.
• Supports up to 16Gbps per pin including 4/8/12Gbps.
• Available with 16 to 64 lanes.
• Supports lane reversal and lane repair (advanced).
• Supports CRC and Retry mechanism.
• Supports runtime Link Testing through Parity, Scrambling/De-scrambling.
• Supports all kind of side band and main band Trainings.
• Supports single and multiple CXL stacks with internal ARB/MUX layer.
• Available with in-built UCIe Retimers.
• Functional coverage for complete UCIe features.
• Monitors, detects and notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
• Supports standard LPIF specification.
• Supports power managements across different layers.

Deliverables

• UCIe Tx/Rx/BFM/Agent
• UCIe Monitor
• UCIe Scoreboard
• Testbench Configurations
• Test Suite (Available in Source code)
  • Basic and Directed Protocol Tests
  • Random Tests or Error Scenario Tests
  • Assertions & Cover Point Tests

Integration Guide, User Manual and Release Notes