25G Ethernet Verification IP
Truechip’s 25G Ethernet Verification IP provides an effective & efficient way to verify the components interfacing with Ethernet interface of an IP or SoC. Truechip’s 25G Ethernet VIP is fully compliant with IEEE standard 802.3by specification. This VIP is light weight with an easy plug -and- play interface so that there is no hit on the design cycle time.
Key Benefits
- Available in native System Verilog (UVM/OVM/ VMM) and Verilog
- Unique development methodology to ensure highest levels of quality
- Availability of Compliance & Regression Test Suites
- 24X5 customer support
- Unique and customizable licensing models
- Exhaustive set of assertions and coverage points with connectivity example for all the components
- Consistency of interface, installation, operation and documentation across all our VIPs
- Provide complete solution and easy integration in IP and SoC environment
Features
- Provides 25 Gb/s as per IEEE std 802.3 and 25G specification revision 2.0
- Supports standard MII interface for 25G
- Supports 25G BASE- KR1/ 25G BASE- CR1
- Supports Auto negotiation for link speed negotiation
- Supports Energy Efficient Ethernet
- Supports clock data recovery(CDR).
- Supports Pause Frame Based Flow Control
- Supports test pattern generation and checking
- Supports Management data Input/output registers.
- Supports full duplex operation.
- Supports AM insertion in 25G RS-FEC sublayer
- Callback support in all Layers to provide user control.
- Rich set of configuration and parameters
- Supports Dynamic as well as Static Error Injection scenarios.
- On the fly protocol checking
- Static and Dynamic assertion.
- Built in Coverage analysis.
- Graphical analyzer to show transactions for easy debugging
Deliverables
- MAC layer
- Reconciliation layer
- PCS layer
- Base-R FEC layer
- Reed Solomon FEC layer
- PMA layer
- PMD layer
- AN layer
- Ethernet 25G layered Monitors and Scoreboard
- Test Environment and Test Suites :
- Basic Tests
- Error Injection Tests
- Assertions & Cover Point Tests
- User Test Suite
- Integration Guide, User Manual and Release Note
- GUI analyser to view simulation packet Flow