DDR3 Verification IP
Truechip's DDR3 Verification IP provides an effective & efficient way to verify the components interfacing with DDR3 interface of an ASIC/FPGA or SoC.
Truechip's DDR3 VIP is fully compliant with Standard DDR3 Version JESD79-3F specifications from JEDEC. This VIP is a light weight VIP with easy plug-and-play interface so that there is no hit on the design time and the simulation time
Key Benefits
- Available in native SystemVerilog (UVM/OVM/VMM) and Verilog
- Unique development methodology to ensure highest levels of quality
- Availability of various Regression Test Suites
- 24X5 customer support
- Unique and customizable licensing models
- Exhaustive set of assertions and cover points with connectivity example for all the components
- Consistency of interface, installation, operation and documentation across the VIP.
- Provide complete solution and easy integration in IP and SoC environment
Features
- Compliant to JEDEC DDR3 SDRAM Specification version JESD79-3F.
- Supports connection to any DDR3 Memory Controller IP communicating with a JESD79-3F compliant DDR3 Memory Model.
- Supports configurable data buses of different sizes (x4, x8, and x16).
- Available in all memory sizes from 512 Mb to 8 Gb.
- DDR PHY interface compatibility.
- Availability of 3DS Memory Model.
- Supports configurable timing parameters and rank associations.
- Supports capturing of all the valid DDR3 commands like Active, Read, Write, Precharge etc.
- Supports Power-up Reset and initialization sequences.
- Supports Precharge Power-Down, Active Power-Down, Self-Refresh operation.
- Reports various timing errors which are used to check any timing violations.
- Provides full user control to enable / disable various types of messages.
- Supports full timing models or bus functional models.
- Multiple instances of Monitor can be instantiated in a Verification Environment to support multiple Chip Selects.
- Supports advanced SystemVerilog features like constrained random testing.
- Supports dynamically configurable modes.
- Strong Protocol Monitor with real time exhaustive programmable checks.
- Supports Dynamic as well as Static Error Injection scenarios.
- On the fly protocol checking using protocol check functions,static and dynamic assertion.
- Built in Coverage analysis.
- Provides a comprehensive user API (callbacks) in Monitor, Controller and Memory Model BFMs.
- Graphical analyser to show transactions for easy debugging
Deliverables
- DDR3-SDRAM Model
- DDR3 Monitor & Scoreboard
- DDR3 Memory Controller BFM/Agent
- DDR3 PHY BFM model
- DDR3 PHY Monitor and Scoreboard
- Test-Bench Configurations
- Test Suite (Available in Source code)
- Basic Protocol Tests
- Directed & Random Tests
- Assertions & Cover Point Tests
- Integration Guide, User Manual and Release Notes
