Design Verification
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Functional Verification Ethernet Verification IP

eMMC v 5.1

Products >> Verification IP >> eMMC v 5.1

eMMC 5.1 verification IP

Truechip's eMMC 5.1 verification IP provides effective and efficient way to verify the component interfacing with Emmc interface of an ASIC / FPGA / SOC.

Truechip's eMMC verification IP is fully complied with standard Emmc version JESD84-B51 from JEDEC. This VIP is a Light Weight VIP with easy plug and play features.

Key Benefits

  • Available in native System Verilog (UVM/OVM/VMM) and Verilog.
  • Unique development methodology to ensure highest levels of quality.
  • Availability of Compliance & Regression Test Suites.
  • 24X5 customer support
  • Unique and customizable licensing models.
  • Exhaustive set of assertions and coverage points with connectivity example for all the components.
  • Consistency of interface, installation, operation and documentation across all our VIPs.
  • Provide complete solution and easy integration in IP and SoC environment.


  • Compliant to JEDEC Emmc version JESD84 - B51.
  • Supports Emmc devices from all leading vendors.
  • Supports configuration for both host and device.
  • Support all data widths 1x ,4x and 8x.
  • Supports all speed modes (Low speed / High Speed).
  • Support both Single and multiple block transfers.
  • Supports Tuning and general purpose commands.
  • Supports Lock and Unlock features.
  • Supports Block read and block write.
  • Supports device density of Greater than equal to 2GB.
  • Supports both Normal and alternate boot operation.
  • Supports sleep modes and Reliable Write.
  • Supports Write Protection mechanism.
  • Supports Multiple Partitions ( Boot area / user area / general purpose partion)
  • Support for both SDR and DDR.
  • Supports Data removal commands Erase / Trim / Santize / Discard.
  • Supports Secure Erase/TRIM.
  • Supports Replay Protect Memory Block.
  • Supports Background Operations.
  • Supports High Priority Interrupt.
  • Supports High Speed Mode (HS200).
  • Supports Enhanced Partition Types.
  • Supports Power Off Notifications & Packed Commands.
  • Supports Data tagging & Device Capacity.
  • Supports Extended Security Commands.
  • Supports High Speed Mode (HS400).
  • Supports Secure Removal Type & Enhanced Data Strobe.
  • Supports Partitioning feature & Bus testing.
  • Supports Power saving sleep mode.
  • Support byte and Block Mode Operations.
  • Support for full-timing as well as behavioral versions in one model.
  • Supports for all timing delay ranges in one model min and max.
  • Reports various timing errors, which can be used to check any timing violation.
  • Provides full control to the user to enable / disable various types of messages.
  • Supports advanced System verilog features like constrained random testing.
  • Supports dynamically configurable modes.
  • Strong protocol monitor with real time exhaustive programmable check.
  • Supports Dynamic as well as static error injection scenario.
  • Built in coverage analysis.
  • Provides a comprohensive user API (call backs) in monitor, host and device controller models /BFM
  • Graphical analyser to show transaction for easy debugging.


  • eMMC Host controller BFM / Agent
  • eMMC Device Controller / Memory BFM/DUT
  • eMMC Monitor
  • eMMC Scoreboard
  • Test Bench Configurations
  • Test suite available in source code
    • Basic Protocol test
    • Directed and random test
    • Assertion and cover point test
  • Integration guide / User Manual /release notes
  • GUI analyzer to view simulation packet flow
Download the Product Brochure from here