HMC2 Verification IP

Truechip's HMC Verification IP provides an effective & efficient way to verify the HMC components of an ASIC/FPGA or SoC i.e. Host or Device.  Truechip's HMC VIP is fully compliant with Standard HMC Version 2.0 specifications from HMCC. This VIP is a light weight VIP with easy plug-and-play interface so that there is no hit on the design time and the simulation time.

Key Benefits

• Available in native SystemVerilog (UVM/OVM/VMM) and Verilog
• Unique development methodology to ensure highest levels of quality
• Availability of Compliance & Regression Test Suites
• 24X5 customer support
• Unique and customizable licensing models
• Exhaustive set of assertions and cover points with connectivity example for all the components
• Consistency of interface, installation, operation and documentation across all our VIPs
• Provide complete solution and easy integration in IP and SoC environment

Features

• Compliant with Standard HMC Version 2.0 specification.
• Supports 4GB configuration - 256 memory banks and 8GB configuration – 512 memory banks.
• Supports Closed-bank memory architecture.
• Supports Built-in memory controller for each vault – Automatic refresh control over all temperatures.
• Supports internal ECC data correction.
• Supports advanced RAS features including data scrubbing.
• Supports Post-assembly repair capability.
• Supports In-field repair for ultimate reliability.
• supports 16 Lane(Full width) , 8 Lane(Half width), 4 Lane(Quarter width) full duplex serialized Link.
• Supports PRBS15 as well as PRBS31 scrambler/descrambler Modes.
• Supports Up to 320 GB/s effective bandwidth.
• Packet based data/command interface.
• Supports 16,32,48,64,80,96,112,128 and 256 byte references per request.
• Supports Error detection for packets with automatic retry.
• Power Management supported per link.
• Reports various error signals, which can be used to check for any error.
• Provides full control to the user to enable / disable various types of messages.
• Supports full timing models or bus functional models.
• Supports advanced SystemVerilog features like constrained random testing.
• Supports dynamically configurable modes.
• Strong Protocol Monitor with real time exhaustive programmable checks.
• Supports Dynamic as well as Static Error Injection scenarios.
• On the fly protocol checking using protocol check functions, static and dynamic assertion.
• Built in Coverage analysis.
• Provides a comprehensive user API (callbacks) in Monitor, Controller and Memory Model BFMs.
• Graphical analyser to show transactions for easy debugging.

Deliverables

• HMC Controller BFM
• HMC Device
• HMC Monitor and Scoreboard
• Test-Bench Configurations
• Test Suite (Available in Source code)
  • Basic Protocol Tests
  • Directed & Random Tests
  • Error Injection Tests
  • Assertions & Cover Point Tests
• Integration Guide, User Manual and Release Note