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Products >> Verification IP >> LIN

LIN Verification IP

Truechip's LIN Verification IP provides an effective & efficient way to verify the LIN components of an IP or SoC. Truechip's LIN VIP is fully compliant with LIN Specification versions 1.3, 2.0, 2.1, and 2.2a. The VIP is lightweight with easy plug-and-play components so that there is no hit on the design cycle time 

Key Benefits

  •  Available in native System Verilog (UVM/OVM/ VMM) and Verilog
  • Unique development methodology to ensure the highest levels of quality
  • Availability of Compliance & Regression Test Suites
  • 24X5 customer support
  • Unique and customizable licensing models
  • Exhaustive set of assertions and coverage points with connectivity examples for all the components
  • Consistency of interface, installation, operation, and documentation across all our VIPs
  • Provide complete solutions and easy integration in IP and SoC environment


  • Adherent to LIN 1.3, 2.0, 2.1, 2.2a Specification and ISO 17987 (Conformance test plan).
  • Supports test cases as per standard.
  • Supports all types of frames.
    • Unconditional frames
    • Event-Triggered Frames
    • Sporadic frames
    • Diagnostic frames
    • Reserved frames
  • Supports recommended bit rates for operation.
  • Supports LIN with Classic Checksum & Advanced Checksum.
  • Tracks MTEC/MREC error counter and fault confinement.
  • Callbacks in master, slave and monitor for user processing of data.
  • Complete LIN functionality.
  • Supports cluster go-to-sleep command, bus idle to sleep, and wake-up commands.
  • Supports Collision Resolving.
  • Supports Half a Duplex of operations.
  • Supports constraints Randomization.
  • Supports frame schedule table.
  • Supports all types of error insertion and detection.
    • Break Field error
    • PID start/stop error
    • Parity Error
    • Checksum error
    • Diagnostic frame error
    • Bit error
    • Data start/stop error
    • Identifier parity errors
    • Slaves not responding to errors
    • Inconsistent Synch Field errors
    • Physical Bus errors
  • Functional coverage for complete LIN features.
  • Monitors detects, and notifies the testbench of significant events.
  • Status counters for various events on the bus.
  • LIN Verification IP comes with a complete test suite to test every feature of LIN specification and Conformance test plan ISO 17987


  • LIN Master/Salve/BFM/Agent
  • LIN Monitor
  • LIN Scoreboard
  • Testbench Configurations
  • Test Suite (Available in Source code)
    • Basic and Directed Protocol Tests
    • Random Tests
    • Error Scenario Tests
    • Assertions & Cover Point Tests
  • Integration Guide, User Manual, and Release Notes
Download the Product Brochure from here