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NoC Silicon IP

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Crossbar Verification IP

NoC Mesh Silicon IP

NoC Mesh Silicon IP

Truechip's NoC IP provides chip designers and architects with an efficient way to connect multiple protocol bus protocol supportive devices with reduced latency, power, and area. NoC Silicon IP also helps to reduce the usage of interconnecting wires and resources inside the chip.

Key Benefits

  • Available in native Verilog (RTL)
  • Linting, Synthesis, CDC, RDC are cleaned up.
  • 100% Code coverage
  • Verified with an expert team using comprehensive and Regression Test Suites.
  • Consistency of interface, installation, operation, and documentation across all our Ips
  • Easy GUI based integration and configuration technique
  • 24X5 customer support
  • Unique and customizable licensing models


  • Noc Mesh Features
    • Complex network with acyclic agent graph (DAG). Layered and parallel NOC is also supported.
    • Robust routing algorithm to traverse data in earliest possible manner
    • Any number of master and slave port is supported. Each port can be configured individually
    • Network Interface block can be separated
    • AMBA AXI 3, 4, 4-Lite, 4-Stream, 5, 5-Lite, 5-Stream, AMBA AHB3-Lite,5, AMBA APB 2,3,4,5. TileLink Tl-UL, Tl-UH
    • Additional connections for reducing latency
    • Dead lock avoidance guarantee
    • Each node can receive and send transaction from different nodes at a time
    • Configurable Node storage capacity, default - 16 Per channel's
    • Configurable memory map for different access types of memory regions
    • Support for different protocol for master and slave port interface.
    • Each port data width can be different. Apart from data, other protocol 1supported signal can also different width.
    • Early response and interrupt generation possible
    • Merging and breaking both possible on transfers
    • Support different phase shifted frequencies for each Master & Slaves
    • Clock enable disable mechanism
    • QoS Supported: Port priority, Programmable register, Keeper count
    • Both Little and high endianness is supported
    • Register slice for asynchronous interface is supported
    • Support physical address conversion through NOC
    • Within minimum latency req or rsp can propagate through NoC

Noc Port Features

  • Per port data width and protocol selection available
  • Configurable access methods, Port security and privilege option supported
  • Configurable Default slave and Port Priority supported
  • Different protocol with different phase shifted clock supported for each port
  • Atomic transaction, NSAID signalling, Read data chunking, Interleaving support, Out of order transfer, Exclusive supports in AXI port
  • Secure Transfer
  • Beat Transfer
  • Non contiguous address
  • Enable buffering
  • Arithmetic and logical transfer
  • Back to back transfer supports in AHB
  • Each transactions are marked with unique ID to identify the packet in Mesh


  • NoC Matrix (Crossbar/Mesh) & NoC Port (AXI/AHB/APB/Tilelink)
  • Ip generator & config tool
  • Verilog Test Environment with Verilog Testcases
  • CDC constraints file (.sdc)
  • IP analysis reports:
    • Linting report
    • Synthesis report
    • CDC report
  • Simulation script
  • IP Block Guide
  • IPG Guide