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NoC Silicon IP

Products >> Silicon IPs >> NoC Silicon IP

NoC Silicon IP

Truechip's NoC IP provides chip designers and architects with an efficient way to connect multiple devices which support different types of bus interfaces and working on different frequency. IP is available in two topologies Crossbar and Mesh. NoC Silicon IP also helps to reduce the usage of interconnecting wires and resources inside the chip.


Key Benefits

  • Available in negative Verilog (RTL).
  • Lintin, Synthesis, CDC, RDC are cleaned up.
  • Verified with an expert team using comprehensive and Regression Test Suites.
  • Consistency of interface, installation, operation, and documentation across all our IPs.
  • Easy GUI based integration and configuration technique
  • 24X5 customer support
  • Unique and customizable licensing models


  • Complex network with acyclic agent graph (DAG). Layered and parallel NOC is also supported.
  • Any number of master and slave port is supported. Each port can be configured individually.
  • AMBA AHB3-Lite,5; AMBA AXI 3, 4, 4-Lite,4-Stream, 5,5-Lite,5-Stream, AMBA APB 2,3,4,5 TileLink Tl-UL, Tl-UH
  • Configurable memory map for different access types of memory regions.
  • Support for different protocol for master and slave port interface.
  • Each port data width can be different. Apart from data, other protocol supported signal can also different width.
  • Early response possible
  • Support different phase shifteded frequencies for each Master and Slaves
  • Port priority, Programmable register, Keeper count
  • Support physical address conversion through NOC
  • Within minimum latency req or rsp can propagate through NoC
  • Both little & high endianness is supported
  • Interleaving support, Out of order transfer , Exclusives supports in AXI port
  • Secure Transfer
  • Beat Transfer
  • Non contiguous address
  • Enable buffering
  • Arithmetic and logical transfer
  • Back to back transfer supports in AHB


  • NoC Matrix (Crossbar/Mesh) & NoC Port (AXI/AHB/APB/Tilelink)
  • IP generator & config tool
  • Verilog Test Environment with Verilog Testcases
  • IP analysis reports​​​
    • ​Linting report
    • Synthesis report
  • IP-XACT RDL generated address map
  • Simulation script
  • IP Block Guide
  • Quick Start Guide

Download the Product Brochure from here