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NoC Silicon IP

Products >> Silicon IPs >> NoC Silicon IP

NoC Silicon IP

Truechip's NoC Silicon IP provides chip designers and architects with an efficient way to connect multiple TileLink based master and slave devices with reduced latency, power, and area. NoC Silicon IP also helps to reduce the usage of interconnecting wires and resources inside the chip.

 

Key Benefits

  • Available in native Verilog (RTL).
  • Unique development RTL coding technique to ensure the highest levels of quality for lower latency, highest throughput and lesser area.
  • Synthesis & CDC are clean up.
  • Verified with expert team using comprehensive and Regression Test Suites.
  • Consistency of interface, installation, operation, and documentation across all our IPs
  • 24X5 customer support
  • Unique and customizable licensing models

 

Features

  • Easy to integrate the NoC Silicon IP using interface
  • N master and M slave ports based on customer requirement
  • Supports wide range of memory map.
  • Support for different characteristics of addresses like READ-ONLY, NO-ACCESS, PRIVILAGE-ACCESS etc.
  • Master selection in priority solver supports fixed as well as round- robin mechanism
  • Support for both little and big endianness
  • Support for different frequency of each master and slave interface
  • Support all types of conformance level with 5 respective channels.
    • TL-UL
    • TL-UH
  • Any type of complex TileLink network which follows the acyclic agent graph (DAG).
  • All parameter Widths like data bus, address, size, sources, sinks are configurable
  • Controllable valid and ready assertion
  • Different modes when ready are not asserted before starting burst. 
  • A configurable number of cycles for bounded busy periods. 
  • User can also provide a particular restriction on address
  • Single and burst request and response supported
  • All 3 types of request-response ordering possible.
  • Response on the same cycle
  • Response before the last beat received
  • Response after some delay of received all beats
  • All types of operations are supported as per respective conformance levels.
    • Access
    • Hint
    • Transfer
  • All opcodes and param for request and response messages supported for operations on all five channels.
  • Can work as any node in the graph of position on a tree.
    • Nothing
    • Trunk
    • Tip (with no Branches)
    • Tip (with Branches)
    • Branch
  • Permission transitions are also supported
    • Cap
    • Grow
    • Prune
    • Report

Deliverables

  • NoC Silicon IP RTL
  • Testbench and Sanity Tests
  • User Manual and Integration guide
  • Quick start guide
  • TruEye Tool for debug (optional)
  • Full Verification IP for TileLink (optional)
Download the Product Brochure from here