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Gen 4

Products >> Verification IP >> Gen 4

PCIe Gen 4 Verification IP

Truechip's PCIe Gen4 Verification IP provides an effective & efficient way to verify the components interfacing with PCIe Gen4 interface of an IP or SoC

Truechip's PCIe Gen4 VIP is fully compliant with latest PCI Express Gen4 specifications. This VIP is a light weight with an easy plug-and-play interface so that there is no hit on the design cycle time.

Key Benefits

  • Available in native SystemVerilog (UVM/OVM/VMM) and Verilog
  • Unique development methodology to ensure highest levels of quality
  • 24X5 customer support
  • Unique and customizable licensing models
  • Exhaustive set of assertions and cover points with connectivity example for all the components
  • Consistency of interface, installation, operation and documentation across all our VIPs
  • Provide complete solution and easy integration in IP and SoC environment


  • Compliant with PCI Express Specifications 4.0 v1.0 (16GT/s), 3.0 (8GT/s), 2.0 (5GT/s) and 1.1 (2.5GT/s).
  • Verification IP configurable as PCI express Root Complex and Device Endpoint.
  • Configurable LinkWidth: x1, x2, x4, x8, x12, x16, x32.
  • Configurable pipe width : 8,16,32,64
  • Supports Low Power management LTSSM states - L0s, L1, L2, L1 sub states,PCI- PM, ASPM. 
  • Advanced Error Reporting (AER) with optional Malformed TLP checks, ECRC and TLP Poisoning support.
  • Compliance testing in TL, DLL & PL including power management test-suites.
  • On the fly protocol checking using protocol check functions, static and dynamic assertion.
  • Built in Coverage analysis.
  • Provides a comprehensive user API (callbacks).
  • Graphical ​analyser for all three Layers to show PCIe transactions for easy debugging.
  • Complaint with Pipe specification 4.4.1.
  • Supports scale flow control.
  • Supports simplified replay timer.
  • Supports SR-IOV.
  • Supports lane margining feature.
  • Supports 10-bit Tag as requester as well as completer.
  • Support for ATS with latest ATS Specification revision 1.1.
  • Supports LTR.
  • Supports FLR ( Function Level Reset).


  • PCIe Gen4 Root-Complex/Device-Endpoint
  • PCIe Gen4 BFM/Agents for :
    • PHY Layer
    • Data Link Layer
    • Transaction Layer
    • Register Space
  • PCIe Gen4 Layered Monitor and Scoreboard
  • Test Environment & Test Suite :
    • Basic and Directed Protocol Tests
    • Random Tests
    • Error Scenario Tests
    • Assertions & Cover Point Tests
    • Compliance Tests
  • Integration Guide, User Manual and Release Notes
Download the Product Brochure from here