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USB 3.2/3.1/3.0

Products >> Verification IP >> USB 3.2/3.1/3.0

USB 3.2 with xHCI & Retimer Verification IP

Truechip's USB 3 .2 Verification IP provides an effective & efficient way to verify the components interfacing with USB 3.2 interface of an IP or SoC. Truechip's USB 3.2 VIP is fully compliant with standard SuperSpeedPlus USB specifications from USB-IF. This VIP is a light weight with an easy plug-and-play interface so that there is no hit on the design cycle time

Key Benefits

  • Available in native SystemVerilog (UVM/OVM/VMM) and Verilog
  • Unique development methodology to ensure highest levels of quality
  • Availability of Compliance & Regression Test Suites
  • 24X5 customer support
  • Unique and customizable licensing models
  • Exhaustive set of assertions and coverage points with connectivity example for all the components
  • Consistency of interface, installation, operation and documentation across all our VIPs
  • Provide complete solution and easy integration in IP and SoC environment.


  • Fully compliant with USB 3.2 specification, xHCI 1.1 and PIPE v4.4.1 Specification with backward compatibility to USB 2.0 .
  • Supports USB Type-C.
  • Supports enhanced Retimer block with layered monitors.
  • Supports upto 128 devices including hub and device on any tier level.
  • Supports 15 IN and 15 OUT and 1 control endpoint for each device.
  • Supports all transfer types; Control, Bulk, Bulk Stream, Interrupt with flow control and retry mechanism.
  • Support for pipelined isochronous and Smart Isochronous transfer.
  • Supports out of band active stream list exchange, HIMD and Stream Proposal rejection feature.
  • SuperSpeedPlus supports Simultaneous in Transactions with transaction re-ordering.
  • Supports bursting in all transfer modes (Upto max burst size).
  • SuperSpeedPlus supports Precision Time Measurement(PTM) and LDM protocol.
  • Enhanced traffic and flow control management in link layer.
    • Type 1 And Type 2 traffic Classes.
    • Different Header packet framing for Deferred and Non- Deferred DPH.
  • Supports all compliance pattern for compliance LTSSM state.
  • Support TS1, TS2, TSEQ, SKP Ordered set generation.
  • Support for all power management states (U1, U2, U3).
  • User controlled device attach/ detach function.
  • Provides SSC and ppm support.
  • Configurability to enable required data rate.
  • 128/132 or 8b/10b encoding as per data rate selection.
  • Comprehensive Compliance Test Suite for Protocol, Link, and Physical Layer verification.
  • Call backs support in all Layers to provide user control and error injection.
  • Smart monitor for automatically masking of all types of error injection.
  • On the fly protocol checking using protocol check functions, static and dynamic assertion.
  • Built in coverage analysis.
  • Graphical analyser for all three Layers to show all transactions for easy debugging.


  • USB 3.2 Host/Device
  • USB 3.2 BFM/Agents for :
    • PHY Layer
    • Link Layer
    • Protocol Layer
  • USB 3.2 Layered Monitor and Scoreboard
  • Test Environment & Test Suite :
    • Basic and Directed Protocol Tests
    • Random Tests
    • Error Scenario Tests
    • Assertions & Cover Point Tests
    • Compliance Tests
    • Stress Test suit for protocol layer
  • Integration Guide, User Manual and Release Notes
  • GUI analyser to view simulation packet Flow


Download the Product Brochure from here