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Functional Verification Ethernet Verification IP

Truechip at DVCON US 2017

Truechip at DVCON US 2017

Truechip at DVCON US 2017

02 March, 2017, San Jose - Truechip Solutions, the Comprehensive Verification IP (CVIP) Specialist, announced today that its participation at DVCON 2017 in San Francisco, CA was a great success. There were total of 1051 attendees including, 775 technical conference attendees and 276 exhibitors at 29th DVCON.

The Award for Best Paper Presentation, as voted by conference attendees, went to Stan Sokorac, ARM, Inc. for his presentation titled, “Optimizing Random Test Constraints Using Machine Learning Algorithms.”  Second place was awarded to Eldon Nelson, Intel Corp. for his presentation, “Improving Constrained Random Testing by Achieving Simulation Verification Goals through Objective Functions, Rewinding and Dynamic Seed Manipulation,” and third place was awarded to Honghuang Lin, Zhipeng Ye and Asad Khan, Texas Instruments, Inc. for their presentation, “Machine Learning based PVT Space Coverage and Worst Case Exploration In Analog and Mixed-Signal Design Verification.”

Top honors for Best Poster went to Johannes Schreiner, Felix Willgerodt and Wolfgang Ecker, Infineon Technologies for their poster, “A New Approach for Generating View Generators. ”Second place was awarded to Daniel Hansson and Patrik Granath, Verifyter AB for their poster, “Automatic Debug Down to the Line of Code,” and third place was awarded to Jacob Maas, Nirabh Regmi, Ashish Kulkarni and Krishnan Palaniswami, Microsoft Corp. for their poster, “End to End Formal Verification Strategies for IP Verification.”

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