Are We Ready for PCIe Gen 1, 2 ,3, 4 ...

Last Month Truechip participated at DVCON China 2017 and we got an overwhelming response. We had visitors from across the globe and we witnessed the increased interest level for Truechip VIPs. We possess a fairy large portfolio of verification IP, but we could see that engineers were very much interested in PCIe. Over a coffee session with our visitor one question was in the air, What’s next after PCIe Gen 4.  I could sense an urge for the need of PCIe successor which was oblivious as tomorrow demands for ultra-high-speed data transmission with least power usage.

Back in time

PCI was created by a group of engineers from INTEL, AMD and other companies, to support complex data transfers. Later it was found that this technology can be extended beyond, and the evolution of PCI express comes into picture. 
PCIe Gen1 supported 2.5 GT/s per lane with max 32 lanes and being bi-directional it could gather 160GT/s. In due course of time this was not satisfying and people were looking for more. Later, PCIe Gen 2 came with 5.0 GT/s per lane. Now the max possible speed was 320GT/s in all 32 lanes. With more complex data, emerged the need for more power and speed. It was a remarkable achievement to achieve 8GT/s in silicon with Gen3. By Now a 30 GB HD movie can be transferred via a PCIe link in less than a second. Still we need more speed, with impeccable accuracy.

The first generation buses include the ISA, EISA, VESA, and Micro Channel buses, while the second generation buses include PCI, AGP, and PCI-X. PCI Express is the third generation high performance I/O bus used to interconnect peripheral devices in applications such as computing and communication platforms. 
PCI Express was created in 2004 to replace PCI. There are different PCI Express specifications and the data transfer rates have been increased to 16GB/s.PCI Express implements a serial, point-to-point type interconnect for communication between two devices. Multiple PCI Express devices are connected via the use of switches which means one can practically connect a large number of devices together in a system.

PCI multi drop parallel bus has limits of performance: it cannot be easily scaled up in frequency or down in voltage; its synchronously clocked data transfer is signal skew limited and the signal routing rules are at the limit for cost-effective FR4 technology. All approaches to pushing these limits to create a higher bandwidth, general-purpose I/O bus result in large cost increases for little performance gain.

PCIe Gen4 gives a whooping speed of 16GT/s per lane. Now we are talking about a transfer of 1TB of data ~30secs. It is a shear example of human excellence in the field of technology.

Addition of new features in PCIe

So here we do a quick look on additions of new features in PCIe versions

Challenges in PCIe Gen4>

1. Enhanced Complexity

2. Reducing Die size

Expecting more, Are we ready?

Yes, To cater the swelling demand of heavy and ultrafast data transfer, PCI express Gen4 seems to be the only solution at present but the requirement is beyond 16 GT/s and we are eyeing for upto 32GT/s. Optical links will prove to be boon which may come up in future. Ofcourse it goes without saying that, lower power usage is definitely the need of the hour since the devices are going to be handheld and we may soon witness a perpetual body wearable which can communicate to other devices and may be even with aliens.

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