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Clocking Architectures in PCI Express

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Clocking Architectures in PCI Express

The PCI Express bus, originally designed for desktop personal computers, is a high-speed serial replacement of the older PCI/PCI-X bus. It is used across a range of applications, including storage devices, networking, communications, cluster interconnect etc. PCI Express is based on point-to-point topology which means separate serial links connect every device to the root complex.

PCI Express protocol provide a flexible solution for data transfers as it can be used as a data interface to flash memory devices, such as memory cards and solid-state drives. Among various advantages of PCIe, it’s scalable bandwidth and flexible clocking tops the list. Here, we will discuss about multiple clocking architectures provided by PCIe along with their advantages and disadvantages.

Clocking Architectures in PCIe

PCIe supports three kinds of clocking as stated below:

1.Common Reference Clock

Common Refclk architecture utilizes the same Refclk for both components (Root-Complex/ Endpoint/Switch) and so it does not introduce any difference in clock between the PCIe components.

2.Separate Reference Clock

2.1 With No SSC(SRNS)

SRNS allows worst case of 600 ppm

2.2 With Independent SSC(SRIS)

SRIS allows 5600 ppm (5000 ssc + 600 ppm) difference for separate REFCLK utilizing independent SSC.

Separate Refclk architecture utilizes the different Refclk for both components (Root-Complex/ Endpoint/Switch) and so it introduces difference in clock between the PCIe Components as shown below:

Challenges when SSC comes into play

Modulation can be carried out on PCIe reference clock with a spread spectrum modulation rate of 30 to 33 kHz and the deviation tolerance of 0% and -0.5% (commonly known as spread spectrum clocking). The modulated clock typically ends up triangular. The overall energy remains unchanged but the peak power is reduced. Use of SSC reduces the EMI level by spreading the radiated energy over a broad range of frequencies.

A spread spectrum signal has the disadvantage of having much higher jitter than the un-modulated signal. Hence, when SSC is used, same Refclk is recommended to be supplied to both devices. Separate Clocking Architecture is therefore not recommended when SSC is required, unless both clocks are synchronized to a common source.

How PCIe tackles with this problem

PCIe protocol has SKP OS (Ordered Sets) that are used to compensate for differences in frequencies between bit rates at two ends of a Link. The Receiver Physical Layer logical sub-block must include elastic buffers which performs this compensation. The interval between SKP Ordered Set transmissions is derived from the absolute value of the Transmit and Receive clock frequency differences.

Drawback of SRIS

The size of elastic buffer is a concern while operating with SRIS clocking architecture as it may need more entries in their elastic buffers as compared to the designs supporting SRNS only, which results in extra latency. This requirement takes into account the extra time it may take to scheduling a SKP Ordered Set if the latter falls immediately after a maximum payload size packet.


The choice of clocking architecture in PCIe plays a vital role in ensuring desired application functionality and performance. Careful understanding and implementation of clocking in PCIe, is important to be compliant with PCIe base specification. Hence, designers must make this choice by taking in account all functional aspects of IP/VIP to meet the laid-out goals. Design compatibility with spread spectrum clocking is one of the major challenge in PCIe. Truechip provides a wide portfolio of clock generators to meet the current requirements of major demanding PCIe Gen 4.0 Verification IP, PCIe Gen 3.0 Verification IP and PCIe Gen 2.1 Verification IP Products.


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