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Functional Verification Ethernet Verification IP

DDR5

Products >> Verification IP >> DDR5

DDR5 Verification IP

Truechip's DDR5 Verification IP provides an effective & efficient way to verify the components interfacing with DDR5 interface of an ASIC/FPGA or SoC.

Truechip's DDR5 VIP is fully compliant with Standard DDR5 specification from JEDEC. This VIP is a light weight with an easy plug-and-play interface so that there is no hit on the design time and the simulation time.

Key Benefits

  • Available in native System Verilog (UVM/OVM/VMM) and Verilog.
  • Unique development methodology to ensure highest levels of quality.
  • Availability of various Regression Test Suites.
  • 24X5 customer support
  • Unique and customizable licensing models.
  • Exhaustive set of assertions and cover points with connectivity example for all the components.
  • Consistency of interface, installation, operation and documentation across all our VIPs.
  • Provide complete solution and easy integration in IP and SoC environment.

Features

  • Compliant to JEDEC DDR5 SDRAM Specification.
  • Supports connection to any DDR5 Memory Controller IP communicating with a JEDEC compliant DDR5 Memory Model.
  • Supports configurable SDRAM addressing of different sizes (x4,x8 and x16).
  • Available in all memory sizes from upto 64 Gb.
  • Supports Data Bus Inversion(DBI).
  • Supports Data Masking(DM).
  • Supports Cyclic Redundancy Check (CRC)
  • Support for all speed-grades/speed-bins.
  • Supports Programmable burst lengths.
  • Supports configurable timing parameters and rank associations.
  • Supports capturing all the valid DDR5 commands including Activate, Read Write, Precharge.
  • Supports CA parity for command/address bus.
  • Supports Power-up Reset and initialization sequences.
  • Supports Precharge Power-Down, Active Power-Down, Self-Refresh operation.
  • Reports various timing errors, which can be used to check any timing violations.
  • Provides full control to the user to enable / disable various types of messages.
  • Supports full timing models or bus functional models.
  • Support for Multiple Ranks architecture.
  • Supports advanced SystemVerilog features like constrained random testing.
  • Supports dynamically configurable modes.
  • Strong Protocol Monitor with real time exhaustive programmable checks.
  • Supports Dynamic as well as Static Error Injection scenarios.
  • On the fly protocol checking using protocol check functions, static and dynamic assertion.
  • Built in Coverage analysis.
  • Provides a comprehensive user API (callbacks) in Monitor, Controller and Memory Model BFMs.
  • Graphical analyser to show transactions for easy debugging.

Deliverables

  • DDR5-SDRAM Model
  • DDR5 Monitor & Scoreboard
  • DDR5 Memory Controller BFM/Agent
  • DDR5 PHY BFM model
  • DDR5 Phy Monitor and Scoreboard
  • Test-Bench Configurations
  • Test Suite (Available in Source code)
    • Basic Protocol Tests
    • Directed & Random Tests
    • Assertions & Cover Point Tests
  • Integration Guide, User Manual and Release Notes
Download the Product Brochure from here